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Use 32 bit rather than 16 bit ints for loop vars. No risk of overflow and is actually faster.
author Daniel O'Connor <darius@dons.net.au>
date Thu, 27 Feb 2025 15:24:17 +1030
parents 600a394629e6
children
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1 ;
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2 ; Copyright (c) 2025 Daniel O'Connor
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3 ;
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5 .program dac
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6 .define TRIGGER_IRQ 0
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7 ; Need 1 side set pin, the clock
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8 .side_set 1
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10 PUBLIC init:
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11 ; Clock in a 0 byte
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98880b18bcc1 Reset DAC PIO and use force trigger to do manual trigger.
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12 mov pins, null side 0
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13 nop side 1
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14 ; Wait for start trigger and clear IRQ
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15 wait 1 irq TRIGGER_IRQ side 0
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16 ; Clock DAC and write data from the FIFO
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17 ; DAC clocks data in on the rising clock edge
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18 .wrap_target
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19 out pins 8 side 0 [1]
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20 nop side 1 [1]
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21 .wrap
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23 % c-sdk {
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24 static inline void dac_program_init(PIO pio, uint sm, uint offset, uint pin, uint clkdiv) {
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25 pio_sm_config c = dac_program_get_default_config(offset);
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27 // Set the OUT base pin to the provided `pin` parameter.
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28 // First 8 pins are data, last is clock
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29 sm_config_set_out_pins(&c, pin, 9);
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30 // Set the pin directions to output at the PIO
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31 pio_sm_set_consecutive_pindirs(pio, sm, pin, 9, true);
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32 // Connect these GPIOs to this PIO block
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33 for (int i = 0; i < 9; i++)
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34 pio_gpio_init(pio, pin + i);
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36 // Configure sideset pin to use for clock
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37 sm_config_set_sideset_pins(&c, pin + 8);
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38
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39 sm_config_set_out_shift(
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40 &c,
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41 true, // Shift-to-right
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42 true, // Autopull enabled
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43 8 // Autopull threshold (bits!)
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44 );
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46 // We only send, so disable the RX FIFO to make the TX FIFO deeper.
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47 sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
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49 sm_config_set_clkdiv(&c, clkdiv);
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51 // Load our configuration (but don't start)
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52 pio_sm_init(pio, sm, offset, &c);
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53 }
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55 static inline uint dac_reset_instr (uint offset) {
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56 // encode a "jmp init side 0" instruction for the state machine
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57 return pio_encode_jmp (offset + dac_offset_init) | pio_encode_sideset (1, 0);
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58 }
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59 %}