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changeset 27:e1d8fe3e418a

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Run PIOs at 1x with delays and sync. Can now use a single trigger to set both DAC & ctrl. DAC [still] jitters against the ctrl though..
author Daniel O'Connor <darius@dons.net.au>
date Wed, 26 Feb 2025 11:03:59 +1030
parents 336f06fa6e47
children 600a394629e6
files ctrl.pio dac.pio modulator.c trigger.pio
diffstat 4 files changed, 44 insertions(+), 43 deletions(-) [+]
line wrap: on
line diff
--- a/ctrl.pio	Tue Feb 25 17:03:51 2025 +1030
+++ b/ctrl.pio	Wed Feb 26 11:03:59 2025 +1030
@@ -2,23 +2,22 @@
 ; Copyright (c) 2025 Daniel O'Connor
 ;
 
+.define TRIGGER_IRQ 0
+
 .program ctrl
-.define DAC_TRIGGER_IRQ 0
-.define CTRL_TRIGGER_IRQ 1
-
 ; Assert all 0s
     mov pins, null
 ; Wait for start trigger and clear IRQ
-    wait 1 irq CTRL_TRIGGER_IRQ
+    wait 1 irq TRIGGER_IRQ
 .wrap_target
-    out pins 8
-    nop
-    out pins 8
-    nop
-    out pins 8
-    nop
-    out pins 8
-    nop
+    out pins 8 [1]
+    nop        [1]
+    out pins 8 [1]
+    nop        [1]
+    out pins 8 [1]
+    nop        [1]
+    out pins 8 [1]
+    nop        [1]
 .wrap
 
 % c-sdk {
@@ -47,8 +46,7 @@
 
     sm_config_set_clkdiv(&c, clkdiv);
 
-    // Load our configuration, and start the program from the beginning
+    // Load our configuration
     pio_sm_init(pio, sm, offset, &c);
-    pio_sm_set_enabled(pio, sm, true);
 }
 %}
--- a/dac.pio	Tue Feb 25 17:03:51 2025 +1030
+++ b/dac.pio	Wed Feb 26 11:03:59 2025 +1030
@@ -3,9 +3,7 @@
 ;
 
 .program dac
-.define DAC_IRQ 0
-.define DAC_TRIGGER_IRQ 0
-.define CTRL_TRIGGER_IRQ 1
+.define TRIGGER_IRQ 0
 ; Need 1 side set pin, the clock
 .side_set 1
 
@@ -13,20 +11,18 @@
     mov pins, null side 0
     nop side 1
 ; Wait for start trigger and clear IRQ
-    wait 1 irq DAC_TRIGGER_IRQ side 0
-; Trigger the control SM
-    irq nowait CTRL_TRIGGER_IRQ side 0
+    wait 1 irq TRIGGER_IRQ side 0
 ; Clock DAC and write data from the FIFO
 ; DAC clocks data in on the rising clock edge
 .wrap_target
-    out pins 8 side 0
-    nop side 1
-    out pins 8 side 0
-    nop side 1
-    out pins 8 side 0
-    nop side 1
-    out pins 8 side 0
-    nop side 1
+    out pins 8 side 0 [1]
+    nop side 1        [1]
+    out pins 8 side 0 [1]
+    nop side 1        [1]
+    out pins 8 side 0 [1]
+    nop side 1        [1]
+    out pins 8 side 0 [1]
+    nop side 1        [1]
 .wrap
 
 % c-sdk {
@@ -57,8 +53,7 @@
 
     sm_config_set_clkdiv(&c, clkdiv);
 
-    // Load our configuration, and start the program from the beginning
+    // Load our configuration
     pio_sm_init(pio, sm, offset, &c);
-    pio_sm_set_enabled(pio, sm, true);
 }
 %}
--- a/modulator.c	Tue Feb 25 17:03:51 2025 +1030
+++ b/modulator.c	Wed Feb 26 11:03:59 2025 +1030
@@ -362,9 +362,9 @@
     }
     dac_sm = pio_claim_unused_sm(pulse_pio, true);
     // Data is GPIO7 to GPIO14, clock is GPIO15
-    // Clock divisor of 2 so it runs at 60MHz and
-    // generates a 30MHz clock
-    dac_program_init(pulse_pio, dac_sm, dac_pio_sm_offset, DACOUT_GPIO, 2);
+    // Clock divisor of 1 but the PIO has delays so it runs at 60MHz
+    // and generates a 30MHz clock
+    dac_program_init(pulse_pio, dac_sm, dac_pio_sm_offset, DACOUT_GPIO, 1);
 
     // Configure a channel to write 32 bits at a time to PIO0
     // SM0's TX FIFO, paced by the data request signal from that peripheral.
@@ -398,7 +398,7 @@
       __breakpoint();
     }
     ctrl_sm = pio_claim_unused_sm(pulse_pio, true);
-    ctrl_program_init(pulse_pio, ctrl_sm, ctrl_pio_sm_offset, CTRLOUT_GPIO, 2);
+    ctrl_program_init(pulse_pio, ctrl_sm, ctrl_pio_sm_offset, CTRLOUT_GPIO, 1);
 
     // Configure a channel to write 32 bits at a time to PIO0
     // SM0's TX FIFO, paced by the data request signal from that peripheral.
@@ -427,9 +427,19 @@
       __breakpoint();
     }
     uint trigger_sm = pio_claim_unused_sm(pulse_pio, true);
-    trigger_program_init(pulse_pio, trigger_sm, trigger_pio_sm_offset, TRIGIN_GPIO, 2);
+    trigger_program_init(pulse_pio, trigger_sm, trigger_pio_sm_offset, TRIGIN_GPIO, 1);
 #endif
 
+    // Start & sync all state machines
+    // This is necessary to avoid any jitter and to make the
+    // trigger sync work correctly
+    pio_enable_sm_mask_in_sync(pulse_pio,
+			       1u << dac_sm |
+			       1u << ctrl_sm |
+#ifdef WITH_TRIGGER
+			       1u << trigger_sm
+#endif
+			       );
     //
     // Setup PWM
     // Used here to output a trigger which gets fed back into the trigger SM
@@ -439,8 +449,8 @@
     // could further subdivide in the IRQ handler
     pwm_config c = pwm_get_default_config();
     pwm_config_set_clkdiv_int(&c, 250);
-    // 8Hz
-    pwm_config_set_wrap(&c, 60000 - 1);
+    // 80Hz
+    pwm_config_set_wrap(&c, 6000 - 1);
 
     gpio_set_function(TRIGOUT_GPIO, GPIO_FUNC_PWM);
 
--- a/trigger.pio	Tue Feb 25 17:03:51 2025 +1030
+++ b/trigger.pio	Wed Feb 26 11:03:59 2025 +1030
@@ -3,8 +3,7 @@
 ;
 
 .program trigger
-.define DAC_TRIGGER_IRQ 0
-.define CTRL_TRIGGER_IRQ 1
+.define TRIGGER_IRQ 0
 ; Use 1 side set pin for debugging
 .side_set 1
 
@@ -13,8 +12,8 @@
     wait 0 pin 0 side 0
 ; Wait for rising edge
     wait 1 pin 0 side 0
-; Signal DAC SM (which will trigger the control one)
-    irq nowait DAC_TRIGGER_IRQ side 1
+; Signal DAC & ctrl SMs
+    irq nowait TRIGGER_IRQ side 1
 .wrap
 
 % c-sdk {
@@ -37,8 +36,7 @@
 
     sm_config_set_clkdiv(&c, clkdiv);
 
-    // Load our configuration, and start the program from the beginning
+    // Load our configuration
     pio_sm_init(pio, sm, offset, &c);
-    pio_sm_set_enabled(pio, sm, true);
 }
 %}