Mercurial > ~darius > hgwebdir.cgi > modulator
diff dac.pio @ 28:600a394629e6
Use 8 bit auto pull otherwise the PIOs jitter (due to DMA contention I guess?)
Don't need to unroll the PIO loops.
Create PIo function to reset each PIO.
Check the DMA IRQ is for us - we get unknown IRQs which need to be ignored or things break.
author | Daniel O'Connor <darius@dons.net.au> |
---|---|
date | Thu, 27 Feb 2025 13:58:37 +1030 |
parents | e1d8fe3e418a |
children |
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--- a/dac.pio Wed Feb 26 11:03:59 2025 +1030 +++ b/dac.pio Thu Feb 27 13:58:37 2025 +1030 @@ -7,6 +7,7 @@ ; Need 1 side set pin, the clock .side_set 1 +PUBLIC init: ; Clock in a 0 byte mov pins, null side 0 nop side 1 @@ -17,12 +18,6 @@ .wrap_target out pins 8 side 0 [1] nop side 1 [1] - out pins 8 side 0 [1] - nop side 1 [1] - out pins 8 side 0 [1] - nop side 1 [1] - out pins 8 side 0 [1] - nop side 1 [1] .wrap % c-sdk { @@ -38,22 +33,27 @@ for (int i = 0; i < 9; i++) pio_gpio_init(pio, pin + i); + // Configure sideset pin to use for clock + sm_config_set_sideset_pins(&c, pin + 8); + sm_config_set_out_shift( &c, true, // Shift-to-right true, // Autopull enabled - 32 // Autopull threshold (bits!) + 8 // Autopull threshold (bits!) ); - // Configure sideset pin to use for clock - sm_config_set_sideset_pins(&c, pin + 8); - // We only send, so disable the RX FIFO to make the TX FIFO deeper. sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX); sm_config_set_clkdiv(&c, clkdiv); - // Load our configuration + // Load our configuration (but don't start) pio_sm_init(pio, sm, offset, &c); } + +static inline uint dac_reset_instr (uint offset) { + // encode a "jmp init side 0" instruction for the state machine + return pio_encode_jmp (offset + dac_offset_init) | pio_encode_sideset (1, 0); +} %}