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annotate libs/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c @ 0:c59513fd84fb

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Initial commit of STM32 test code.
author Daniel O'Connor <darius@dons.net.au>
date Mon, 03 Oct 2011 21:19:15 +1030
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1 /**
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2 ******************************************************************************
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3 * @file DMA/SPI_RAM/main.c
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4 * @author MCD Application Team
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5 * @version V3.5.0
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6 * @date 08-April-2011
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7 * @brief Main program body
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8 ******************************************************************************
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9 * @attention
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10 *
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11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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17 *
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18 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
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19 ******************************************************************************
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20 */
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21
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22 /* Includes ------------------------------------------------------------------*/
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23 #include "stm32f10x.h"
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24 #include "platform_config.h"
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25 #include "stm32_eval.h"
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26
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27 /** @addtogroup STM32F10x_StdPeriph_Examples
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28 * @{
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29 */
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30
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31 /** @addtogroup DMA_SPI_RAM
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32 * @{
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33 */
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34
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35 /* Private typedef -----------------------------------------------------------*/
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36 typedef enum { FAILED = 0, PASSED = !FAILED} TestStatus;
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37
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38 /* Private define ------------------------------------------------------------*/
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39 #define BufferSize 32
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40 #define CRCPolynomial 7
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41
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42 /* Private macro -------------------------------------------------------------*/
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43 /* Private variables ---------------------------------------------------------*/
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44 SPI_InitTypeDef SPI_InitStructure;
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45 DMA_InitTypeDef DMA_InitStructure;
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46 uint8_t SPI_MASTER_Buffer_Rx[BufferSize], SPI_SLAVE_Buffer_Rx[BufferSize];
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47 volatile uint8_t SPI_MASTERCRCValue = 0, SPI_SLAVECRCValue = 0;
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48 volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED;
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49
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50 uint8_t SPI_MASTER_Buffer_Tx[BufferSize] = {0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,
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51 0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10,
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52 0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,
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53 0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F,0x20};
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54
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55 uint8_t SPI_SLAVE_Buffer_Tx[BufferSize] = {0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,
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56 0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,0x60,
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57 0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,
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58 0x69,0x6A,0x6B,0x6C,0x6D,0x6E,0x6F,0x70};
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59
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60 /* Private function prototypes -----------------------------------------------*/
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61 void RCC_Configuration(void);
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62 void GPIO_Configuration(void);
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63 TestStatus Buffercmp(uint8_t* pBuffer, uint8_t* pBuffer1, uint16_t BufferLength);
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64
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65 /* Private functions ---------------------------------------------------------*/
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66
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67 /**
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68 * @brief Main program
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69 * @param None
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70 * @retval None
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71 */
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72 int main(void)
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73 {
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74 /*!< At this stage the microcontroller clock setting is already configured,
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75 this is done through SystemInit() function which is called from startup
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76 file (startup_stm32f10x_xx.s) before to branch to application main.
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77 To reconfigure the default setting of SystemInit() function, refer to
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78 system_stm32f10x.c file
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79 */
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80
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81 /* Configure the STM32_EVAL LED */
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82 STM_EVAL_LEDInit(LED1);
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83 STM_EVAL_LEDInit(LED2);
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84 /* Turn Off LED1 and LED2 */
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85 STM_EVAL_LEDOff(LED1);
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86 STM_EVAL_LEDOff(LED2);
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87
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88 /* System Clocks Configuration */
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89 RCC_Configuration();
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90
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91 /* Configure the GPIO ports */
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92 GPIO_Configuration();
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93
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94 /* SPI_MASTER configuration ------------------------------------------------*/
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95 SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
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96 SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
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97 SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
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98 SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
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99 SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
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100 SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
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101 SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8;
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102 SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
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103 SPI_InitStructure.SPI_CRCPolynomial = CRCPolynomial;
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104 SPI_Init(SPI_MASTER, &SPI_InitStructure);
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105
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106 /* SPI_SLAVE configuration -------------------------------------------------*/
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107 SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
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108 SPI_Init(SPI_SLAVE, &SPI_InitStructure);
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109
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110 /* SPI_MASTER_Rx_DMA_Channel configuration ---------------------------------*/
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111 DMA_DeInit(SPI_MASTER_Rx_DMA_Channel);
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112 DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SPI_MASTER_DR_Base;
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113 DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPI_MASTER_Buffer_Rx;
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114 DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
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115 DMA_InitStructure.DMA_BufferSize = BufferSize;
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116 DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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117 DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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118 DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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119 DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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120 DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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121 DMA_InitStructure.DMA_Priority = DMA_Priority_High;
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122 DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
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123 DMA_Init(SPI_MASTER_Rx_DMA_Channel, &DMA_InitStructure);
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124
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125 /* SPI_MASTER_Tx_DMA_Channel configuration ---------------------------------*/
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126 DMA_DeInit(SPI_MASTER_Tx_DMA_Channel);
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127 DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SPI_MASTER_DR_Base;
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128 DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPI_MASTER_Buffer_Tx;
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129 DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
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130 DMA_InitStructure.DMA_Priority = DMA_Priority_Low;
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131 DMA_Init(SPI_MASTER_Tx_DMA_Channel, &DMA_InitStructure);
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132
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133 /* SPI_SLAVE_Rx_DMA_Channel configuration ----------------------------------*/
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134 DMA_DeInit(SPI_SLAVE_Rx_DMA_Channel);
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135 DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SPI_SLAVE_DR_Base;
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136 DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPI_SLAVE_Buffer_Rx;
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137 DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
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138 DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
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139 DMA_Init(SPI_SLAVE_Rx_DMA_Channel, &DMA_InitStructure);
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140
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141 /* SPI_SLAVE_Tx_DMA_Channel configuration ----------------------------------*/
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142 DMA_DeInit(SPI_SLAVE_Tx_DMA_Channel);
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143 DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SPI_SLAVE_DR_Base;
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144 DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPI_SLAVE_Buffer_Tx;
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145 DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
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146 DMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
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147 DMA_Init(SPI_SLAVE_Tx_DMA_Channel, &DMA_InitStructure);
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148
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149 /* Enable SPI_MASTER DMA Tx request */
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150 SPI_I2S_DMACmd(SPI_MASTER, SPI_I2S_DMAReq_Tx, ENABLE);
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151 /* Enable SPI_MASTER DMA Rx request */
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152 SPI_I2S_DMACmd(SPI_MASTER, SPI_I2S_DMAReq_Rx, ENABLE);
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153 /* Enable SPI_SLAVE DMA Tx request */
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154 SPI_I2S_DMACmd(SPI_SLAVE, SPI_I2S_DMAReq_Tx, ENABLE);
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155 /* Enable SPI_SLAVE DMA Rx request */
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156 SPI_I2S_DMACmd(SPI_SLAVE, SPI_I2S_DMAReq_Rx, ENABLE);
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157
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diff changeset
158 /* Enable SPI_MASTER CRC calculation */
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159 SPI_CalculateCRC(SPI_MASTER, ENABLE);
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diff changeset
160 /* Enable SPI_SLAVE CRC calculation */
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161 SPI_CalculateCRC(SPI_SLAVE, ENABLE);
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162
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163 /* Enable SPI_SLAVE */
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164 SPI_Cmd(SPI_SLAVE, ENABLE);
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165 /* Enable SPI_MASTER */
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166 SPI_Cmd(SPI_MASTER, ENABLE);
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167
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diff changeset
168 /* Enable DMA channels */
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169 DMA_Cmd(SPI_MASTER_Rx_DMA_Channel, ENABLE);
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170 DMA_Cmd(SPI_SLAVE_Rx_DMA_Channel, ENABLE);
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171 DMA_Cmd(SPI_SLAVE_Tx_DMA_Channel, ENABLE);
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172 DMA_Cmd(SPI_MASTER_Tx_DMA_Channel, ENABLE);
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173
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174 /* Transfer complete */
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175 while(!DMA_GetFlagStatus(SPI_MASTER_Rx_DMA_FLAG));
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176 while(!DMA_GetFlagStatus(SPI_SLAVE_Rx_DMA_FLAG));
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177 while(!DMA_GetFlagStatus(SPI_SLAVE_Tx_DMA_FLAG));
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178 while(!DMA_GetFlagStatus(SPI_MASTER_Tx_DMA_FLAG));
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179
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diff changeset
180 /* Wait for SPI_MASTER data reception: CRC transmitted by SPI_SLAVE */
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181 while(SPI_I2S_GetFlagStatus(SPI_MASTER, SPI_I2S_FLAG_RXNE) == RESET);
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182 /* Wait for SPI_SLAVE data reception: CRC transmitted by SPI_MASTER */
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183 while(SPI_I2S_GetFlagStatus(SPI_SLAVE, SPI_I2S_FLAG_RXNE) == RESET);
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184
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185 /* Check the correctness of written dada */
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186 TransferStatus1 = Buffercmp(SPI_SLAVE_Buffer_Rx, SPI_MASTER_Buffer_Tx, BufferSize);
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187 TransferStatus2 = Buffercmp(SPI_MASTER_Buffer_Rx, SPI_SLAVE_Buffer_Tx, BufferSize);
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188 /* TransferStatus1, TransferStatus2 = PASSED, if the data transmitted and received
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189 are correct */
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190 /* TransferStatus1, TransferStatus2 = FAILED, if the data transmitted and received
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191 are different */
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192
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193 /* Test on the SPI_MASTER CRCR ERROR flag */
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194 if ((SPI_I2S_GetFlagStatus(SPI_MASTER, SPI_FLAG_CRCERR)) != RESET)
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195 {
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196 TransferStatus1 = FAILED;
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197 }
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198 /* Test on the SPI_SLAVE CRCR ERROR flag */
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199 if ((SPI_I2S_GetFlagStatus(SPI_SLAVE, SPI_FLAG_CRCERR)) != RESET)
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200 {
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201 TransferStatus2 = FAILED;
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202 }
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203
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diff changeset
204 /* Read SPI_MASTER received CRC value */
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205 SPI_MASTERCRCValue = SPI_I2S_ReceiveData(SPI_MASTER);
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206 /* Read SPI_SLAVE received CRC value */
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207 SPI_SLAVECRCValue = SPI_I2S_ReceiveData(SPI_SLAVE);
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208
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diff changeset
209 if (TransferStatus1 != FAILED)
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diff changeset
210 {
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211 /* OK */
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diff changeset
212 /* Turn on LD1 */
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213 STM_EVAL_LEDOn(LED1);
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214 }
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diff changeset
215 else
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diff changeset
216 {
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diff changeset
217 /* KO */
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diff changeset
218 /* Turn Off LD1 */
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219 STM_EVAL_LEDOff(LED1);
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220 }
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diff changeset
221
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diff changeset
222 if (TransferStatus2 != FAILED)
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diff changeset
223 {
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diff changeset
224 /* OK */
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diff changeset
225 /* Turn on LD2 */
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diff changeset
226 STM_EVAL_LEDOn(LED2);
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diff changeset
227 }
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diff changeset
228 else
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diff changeset
229 {
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diff changeset
230 /* KO */
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diff changeset
231 /* Turn Off LD2 */
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diff changeset
232 STM_EVAL_LEDOff(LED2);
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diff changeset
233 }
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diff changeset
234
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diff changeset
235 while (1)
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diff changeset
236 {
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diff changeset
237 }
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diff changeset
238 }
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239
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
240 /**
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diff changeset
241 * @brief Configures the different system clocks.
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diff changeset
242 * @param None
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diff changeset
243 * @retval None
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diff changeset
244 */
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diff changeset
245 void RCC_Configuration(void)
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diff changeset
246 {
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diff changeset
247 /* PCLK2 = HCLK/2 */
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diff changeset
248 RCC_PCLK2Config(RCC_HCLK_Div2);
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diff changeset
249
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diff changeset
250 /* Enable peripheral clocks ------------------------------------------------*/
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diff changeset
251 /* Enable DMA1 or/and DMA2 clock */
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diff changeset
252 RCC_AHBPeriphClockCmd(SPI_MASTER_DMA_CLK | SPI_SLAVE_DMA_CLK, ENABLE);
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diff changeset
253
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diff changeset
254 #ifdef USE_STM3210C_EVAL
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diff changeset
255 /* Enable GPIO clock for SPI_MASTER and SPI_SLAVE */
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diff changeset
256 RCC_APB2PeriphClockCmd(SPI_MASTER_GPIO_CLK | SPI_SLAVE_GPIO_CLK |
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diff changeset
257 RCC_APB2Periph_AFIO, ENABLE);
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diff changeset
258
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diff changeset
259 /* Enable SPI_MASTER Periph clock */
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diff changeset
260 RCC_APB1PeriphClockCmd(SPI_MASTER_CLK, ENABLE);
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diff changeset
261
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diff changeset
262 #else
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diff changeset
263 /* Enable SPI_MASTER clock and GPIO clock for SPI_MASTER and SPI_SLAVE */
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diff changeset
264 RCC_APB2PeriphClockCmd(SPI_MASTER_GPIO_CLK | SPI_SLAVE_GPIO_CLK |
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diff changeset
265 SPI_MASTER_CLK, ENABLE);
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diff changeset
266 #endif
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diff changeset
267 /* Enable SPI_SLAVE Periph clock */
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diff changeset
268 RCC_APB1PeriphClockCmd(SPI_SLAVE_CLK, ENABLE);
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diff changeset
269 }
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diff changeset
270
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
271 /**
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diff changeset
272 * @brief Configures the different GPIO ports.
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diff changeset
273 * @param None
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diff changeset
274 * @retval None
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diff changeset
275 */
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diff changeset
276 void GPIO_Configuration(void)
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diff changeset
277 {
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diff changeset
278 GPIO_InitTypeDef GPIO_InitStructure;
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diff changeset
279
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diff changeset
280 #ifdef USE_STM3210C_EVAL
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diff changeset
281 /* Enable SPI3 Pins Software Remapping */
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diff changeset
282 GPIO_PinRemapConfig(GPIO_Remap_SPI3, ENABLE);
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diff changeset
283 #endif
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diff changeset
284
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diff changeset
285 /* Configure SPI_MASTER pins: SCK and MOSI */
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diff changeset
286 GPIO_InitStructure.GPIO_Pin = SPI_MASTER_PIN_SCK | SPI_MASTER_PIN_MOSI;
c59513fd84fb Initial commit of STM32 test code.
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287 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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288 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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289 GPIO_Init(SPI_MASTER_GPIO, &GPIO_InitStructure);
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290 /* Configure SPI_MASTER pins: MISO */
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291 GPIO_InitStructure.GPIO_Pin = SPI_MASTER_PIN_MISO;
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292 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
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293 GPIO_Init(SPI_MASTER_GPIO, &GPIO_InitStructure);
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294
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295 /* Configure SPI_SLAVE pins: SCK and MOSI */
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296 GPIO_InitStructure.GPIO_Pin = SPI_SLAVE_PIN_SCK | SPI_SLAVE_PIN_MOSI;
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297 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
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298 GPIO_Init(SPI_SLAVE_GPIO, &GPIO_InitStructure);
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299 /* Configure SPI_SLAVE pins: MISO */
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300 GPIO_InitStructure.GPIO_Pin = SPI_SLAVE_PIN_MISO ;
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301 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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302 GPIO_Init(SPI_SLAVE_GPIO, &GPIO_InitStructure);
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303 }
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304
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305 /**
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306 * @brief Compares two buffers.
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307 * @param pBuffer, pBuffer1: buffers to be compared.
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308 * @param BufferLength: buffer's length
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309 * @retval PASSED: pBuffer identical to pBuffer1
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310 * FAILED: pBuffer differs from pBuffer1
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311 */
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312 TestStatus Buffercmp(uint8_t* pBuffer, uint8_t* pBuffer1, uint16_t BufferLength)
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313 {
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314 while(BufferLength--)
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315 {
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316 if(*pBuffer != *pBuffer1)
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317 {
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318 return FAILED;
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319 }
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320
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321 pBuffer++;
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322 pBuffer1++;
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323 }
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324
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325 return PASSED;
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326 }
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327
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328 #ifdef USE_FULL_ASSERT
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329
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330 /**
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331 * @brief Reports the name of the source file and the source line number
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332 * where the assert_param error has occurred.
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333 * @param file: pointer to the source file name
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334 * @param line: assert_param error line source number
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335 * @retval None
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336 */
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337 void assert_failed(uint8_t* file, uint32_t line)
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338 {
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339 /* User can add his own implementation to report the file name and line number,
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340 ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
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341
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342 /* Infinite loop */
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343 while (1)
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344 {
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345 }
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346 }
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347
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348 #endif
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349
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350 /**
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351 * @}
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352 */
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353
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354 /**
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355 * @}
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356 */
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357
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358 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/