Mercurial > ~darius > hgwebdir.cgi > stm32temp

annotate spiflash.c @ 84:1ea404a7683c

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Ignore cscope files
author Daniel O'Connor <darius@dons.net.au>
date Mon, 02 Mar 2015 14:32:34 +1030
parents 05ba84c7da97
children
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1 #include <stdio.h>
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2 #include <stdint.h>
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3 #include <string.h>
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4 #include <stdlib.h>
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5 #include <assert.h>
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6
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7 #include "stm32f10x.h"
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8 #include "spi.h"
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9 #include "spiflash.h"
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10
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11 #define FL_SELECT() GPIO_ResetBits(GPIOA, GPIO_Pin_4)
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12 #define FL_DESELECT() GPIO_SetBits(GPIOA, GPIO_Pin_4)
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13
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14 const char *flstattbl[] = {
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15 "BUSY",
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16 "WEL",
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17 "BP0",
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18 "BP1",
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19 "BP2",
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20 "BP3",
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21 "AAI",
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22 "BPL"
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23 };
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24
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25 #define RW_IDLE 0
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26 #define RW_RUNNING 1
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27
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28 static int writestate = RW_IDLE;
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29 static int readstate = RW_IDLE;
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30
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31 void
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32 spiflash4kerase(uint32_t addr) {
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33 spiflashenablewrite(); /* Enable writing */
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34
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35 FL_SELECT(); /* Select device */
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36
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37 SPI_WriteByte(FL_4KERASE); /* Send command */
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38 SPI_WriteByte(addr >> 16); /* Send address */
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39 SPI_WriteByte(addr >> 8);
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40 SPI_WriteByte(addr);
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41
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42 FL_DESELECT();
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43
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44 //fputs("4k erase ", stdout);
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45 spiflashwait();
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46 }
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47
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48 void
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49 spiflashwait(void) {
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50 uint8_t cnt;
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51
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52 /* Wait for not BUSY */
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53 for (cnt = 0; (spiflashreadstatus() & FL_BUSY) != 0; cnt++)
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54 ;
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55
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56 //printf("cnt = %d\n", cnt);
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57 }
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58
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59 uint16_t
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60 spiflashreadid(void) {
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61 uint8_t fac, dev;
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62
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63 FL_SELECT(); /* Select device */
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64
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65 SPI_WriteByte(FL_RDID); /* Send command */
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66 SPI_WriteByte(0x00); /* Send address cycles (ID data starts at 0) */
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67 SPI_WriteByte(0x00);
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68 SPI_WriteByte(0x00);
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69 fac = SPI_WriteByte(0x00); /* Read ID */
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70 dev = SPI_WriteByte(0x00);
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71
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72 FL_DESELECT(); /* De-select device */
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73
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74 return fac << 8 | dev;
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75 }
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76
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77 void
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78 spiflashenablewrite(void) {
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79 FL_SELECT(); /* Select device */
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81 SPI_WriteByte(FL_WREN); /* Send command */
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82
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83 FL_DESELECT(); /* De-select device */
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84 }
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85
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86 uint8_t
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87 spiflashreadstatus(void) {
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88 uint8_t status;
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89
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90 FL_SELECT(); /* Select device */
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91
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92 SPI_WriteByte(FL_RDSR); /* Send command */
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93 SPI_WriteByte(0x00); /* Send dummy byte for address cycle */
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94 status = SPI_WriteByte(0x00); /* Read status */
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95
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96 FL_DESELECT(); /* De-select device */
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97
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98 return status;
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99 }
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100
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101 void
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102 spiflashwritestatus(uint8_t status) {
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103 /* Enable status write */
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104 FL_SELECT(); /* Select device */
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105 SPI_WriteByte(FL_EWSR); /* Send command */
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106 SPI_WriteByte(0x00); /* Send data byte */
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107 FL_DESELECT();
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108
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109 /* Actually write status */
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110 FL_SELECT(); /* Re-select device for new command */
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111 SPI_WriteByte(FL_WRSR); /* Send command */
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112 SPI_WriteByte(status); /* Send data byte */
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113 FL_DESELECT(); /* De-select device */
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114 }
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115
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116 uint8_t
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117 spiflashread(uint32_t addr) {
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118 uint8_t data;
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119
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120 FL_SELECT(); /* Select device */
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121
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122 SPI_WriteByte(FL_READ); /* Send command */
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123 SPI_WriteByte(addr >> 16); /* Send address */
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124 SPI_WriteByte(addr >> 8);
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125 SPI_WriteByte(addr);
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126 data = SPI_WriteByte(0x00); /* Read data */
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127
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128 FL_DESELECT(); /* De-select device */
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129
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130 return data;
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131 }
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132
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133 void
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134 spiflashwrite(uint32_t addr, uint8_t data) {
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135 spiflashwait();
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136 spiflashenablewrite(); /* Enable writes */
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137
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138 FL_SELECT(); /* Select device */
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139
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140 SPI_WriteByte(FL_BYTEPROG); /* Send command */
25
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141 SPI_WriteByte(addr >> 16); /* Send address */
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142 SPI_WriteByte(addr >> 8);
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143 SPI_WriteByte(addr);
21
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144 SPI_WriteByte(data); /* Write data */
83
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145
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146 FL_DESELECT(); /* De-select device */
25
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147
21
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148 }
25
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149
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150 /*
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151 * fStream reading looks like so
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152 *
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153 */
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154
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155 void
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156 spiflashstartread(uint32_t addr) {
25
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157 assert(readstate == RW_IDLE);
83
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158
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159 FL_SELECT(); /* Select device */
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160
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161 SPI_WriteByte(FL_READ); /* Send command */
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162 SPI_WriteByte(addr >> 16); /* Send address */
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163 SPI_WriteByte(addr >> 8);
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164 SPI_WriteByte(addr);
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165
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166 readstate = RW_RUNNING;
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167 }
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168
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169 uint8_t
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170 spiflashreadbyte(void) {
25
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171 assert(readstate == RW_RUNNING);
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172 return SPI_WriteByte(0x00); /* Read data */
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173 }
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174
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175 void
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176 spiflashstopread(void) {
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177 assert(readstate == RW_RUNNING);
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178
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179 FL_DESELECT();
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180
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181 readstate = RW_IDLE;
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182 }
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183
83
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184 /*
25
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185 * Auto increment writing looks like so
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186 *
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187 * Enable writing CS, WREN, nCS
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188 * Send start address & first data word CS, AAI + addr + data, nCS
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189 * Send subsequent words wait for nBUSY, CS, AAI + data, nCS
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190 * ...
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191 * Disable writing CS, WRDI, nCS
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192 *
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193 * XXX: EBSY command links SO to flash busy state, I don't think the
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194 * STM32 could sample it without switching out of SPI mode.
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195 */
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196 void
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197 spiflashstartwrite(uint32_t addr, uint16_t data) {
25
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198 assert(writestate == RW_IDLE);
83
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199
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200 spiflashenablewrite(); /* Enable writes */
25
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201
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202 FL_SELECT(); /* Select device */
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203
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204 SPI_WriteByte(FL_AAIWP); /* Send command */
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205 SPI_WriteByte(addr >> 16);
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206 SPI_WriteByte(addr >> 8);
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207 SPI_WriteByte(addr & 0xff); /* Send address */
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208
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209 SPI_WriteByte(data & 0xff); /* Write LSB */
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210 SPI_WriteByte(data >> 8); /* Write MSB */
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211
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212 FL_DESELECT();
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213
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214 writestate = RW_RUNNING;
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215 }
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216
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217 void
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218 spiflashwriteword(uint16_t data) {
25
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219 assert(writestate == RW_RUNNING);
83
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220
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221 //fputs("write word ", stdout);
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222 spiflashwait(); /* Wait until not busy */
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223
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224 FL_SELECT(); /* Select device */
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225
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226 SPI_WriteByte(FL_AAIWP); /* Send command */
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227 SPI_WriteByte(data & 0xff); /* Write LSB */
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228 SPI_WriteByte(data >> 8); /* Write MSB */
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229
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230 FL_DESELECT(); /* De-select device */
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231 }
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232
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233 void
80
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234 spiflashstopwrite(void) {
25
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235 assert(writestate == RW_RUNNING);
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236
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237 //fputs("flash stop write start ", stdout);
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238 spiflashwait(); /* Wait until not busy */
25
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239
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240 FL_SELECT(); /* Select device */
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241
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242 SPI_WriteByte(FL_WRDI); /* Send command */
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243
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244 FL_DESELECT(); /* Deselect device */
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245
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246 //fputs("flash stop write end ", stdout);
80
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247 spiflashwait(); /* Wait until not busy */
25
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248
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249 writestate = RW_IDLE;
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250 }
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251
27
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diff changeset
252 int
80
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diff changeset
253 spiflashreadblock(uint32_t addr, uint32_t len, void *_data) {
83
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254 uint32_t *data = _data;
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diff changeset
255 uint32_t flashcrc, ramcrc, tmp;
27
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diff changeset
256
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257 /* Must be a multiple of 4 due to CRC check */
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258 assert(len % 4 == 0);
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259
80
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diff changeset
260 spiflashstartread(addr);
83
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diff changeset
261 CRC_ResetDR();
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diff changeset
262 for (int i = len; i > 0; i -= 4) {
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diff changeset
263 tmp = spiflashreadbyte() |
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264 spiflashreadbyte() << 8 |
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265 spiflashreadbyte() << 16 |
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266 spiflashreadbyte() << 24;
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267
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268 *data = tmp;
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diff changeset
269 CRC_CalcCRC(tmp);
27
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diff changeset
270 data++;
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271 }
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272
80
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diff changeset
273 flashcrc = spiflashreadbyte();
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diff changeset
274 flashcrc |= spiflashreadbyte() << 8;
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diff changeset
275 flashcrc |= spiflashreadbyte() << 16;
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276 flashcrc |= spiflashreadbyte() << 24;
27
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277
80
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diff changeset
278 spiflashstopread();
27
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diff changeset
279
69
cf9eb08b8b23 CRC a word at a time rather than the whole block (since we are reading/writing a word at a time).
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diff changeset
280 ramcrc = CRC_GetCRC();
83
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diff changeset
281
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282 //printf("RAM CRC 0x%08x Flash CRC 0x%08x\n", (uint)ramcrc, (uint)flashcrc);
69
cf9eb08b8b23 CRC a word at a time rather than the whole block (since we are reading/writing a word at a time).
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283 if (ramcrc == flashcrc)
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284 return 1;
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285 else
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286 return 0;
27
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287 }
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288
70
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289 uint32_t
80
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290 spiflashcrcblock(uint32_t addr, uint32_t len) {
83
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291 uint32_t tmp;
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292
70
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293 assert(len % 4 == 0);
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294
83
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295 CRC_ResetDR();
70
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296
80
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297 spiflashstartread(addr);
83
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298 for (; len > 0; len -= 4) {
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299 tmp = spiflashreadbyte() |
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300 spiflashreadbyte() << 8 |
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301 spiflashreadbyte() << 16 |
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302 spiflashreadbyte() << 24;
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303 CRC_CalcCRC(tmp);
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304 }
80
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305 spiflashstopread();
70
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306
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307 return CRC_GetCRC();
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308 }
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309
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diff changeset
310 int
80
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diff changeset
311 spiflashwriteblock(uint32_t addr, uint32_t len, void *_data) {
27
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312 uint16_t *data = _data;
83
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313 uint32_t crc, vcrc, tmp;
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314
75
85f16813c730 Convert \r\n to \n
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315 //printf("Writing %u bytes to 0x%06x\n", (uint)len, (uint)addr);
83
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316
27
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317 /* Ensure data is
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318 * - 16 bit aligned
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diff changeset
319 * - a multiple of 32 bits in length (for CRCs, the flash only need 16 bits)
83
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diff changeset
320 * - not longer than a sector
27
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321 */
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diff changeset
322 assert(addr % 2 == 0);
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diff changeset
323 assert(len % 4 == 0);
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diff changeset
324 assert(len <= 4096);
83
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diff changeset
325
27
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diff changeset
326 /* Disable write protect */
80
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM.
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diff changeset
327 spiflashwritestatus(0x00);
27
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diff changeset
328
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diff changeset
329 /* Erase sector */
80
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM.
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diff changeset
330 spiflash4kerase(addr);
69
cf9eb08b8b23 CRC a word at a time rather than the whole block (since we are reading/writing a word at a time).
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diff changeset
331
27
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332 /* Write data */
83
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diff changeset
333 CRC_ResetDR();
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diff changeset
334 for (uint i = 0; i < len / 2; i++) {
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diff changeset
335 //printf("0x%04x: %04x\n", i, *data);
27
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diff changeset
336 if (i == 0)
80
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM.
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diff changeset
337 spiflashstartwrite(addr, *data);
27
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diff changeset
338 else
80
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM.
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diff changeset
339 spiflashwriteword(*data);
83
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diff changeset
340
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diff changeset
341 if (i % 2 == 0)
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diff changeset
342 tmp = *data;
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diff changeset
343 else {
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diff changeset
344 tmp |= *data << 16;
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diff changeset
345 CRC_CalcCRC(tmp);
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diff changeset
346 }
27
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diff changeset
347 data++;
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diff changeset
348 }
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diff changeset
349
83
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diff changeset
350 /* Calculate CRC */
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diff changeset
351 crc = CRC_GetCRC();
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diff changeset
352 //printf("CRC is 0x%08x\n", (uint)crc);
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diff changeset
353
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diff changeset
354 /* Write CRC */
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diff changeset
355 spiflashwriteword(crc);
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diff changeset
356 spiflashwriteword(crc >> 16);
70
aaf0603d7f88 Add routine to CRC a block of flash. Use it to verify a flash block write.
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diff changeset
357
83
05ba84c7da97 Add a flash layer for compatibility (in future).
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diff changeset
358 spiflashstopwrite();
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diff changeset
359
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Daniel O'Connor <darius@dons.net.au>
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diff changeset
360 /* Read back and check CRC */
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Daniel O'Connor <darius@dons.net.au>
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diff changeset
361 vcrc = spiflashcrcblock(addr, len);
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Daniel O'Connor <darius@dons.net.au>
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diff changeset
362 //printf("CRC read back as 0x%08x\n", (uint)vcrc);
05ba84c7da97 Add a flash layer for compatibility (in future).
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parents: 80
diff changeset
363 if (vcrc != crc)
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Daniel O'Connor <darius@dons.net.au>
parents: 80
diff changeset
364 return 1;
05ba84c7da97 Add a flash layer for compatibility (in future).
Daniel O'Connor <darius@dons.net.au>
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diff changeset
365 else
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Daniel O'Connor <darius@dons.net.au>
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diff changeset
366 return 0;
27
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to
Daniel O'Connor <darius@dons.net.au>
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diff changeset
367 }
80
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM.
Daniel O'Connor <darius@dons.net.au>
parents: 75
diff changeset
368
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM.
Daniel O'Connor <darius@dons.net.au>
parents: 75
diff changeset
369 void
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM.
Daniel O'Connor <darius@dons.net.au>
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diff changeset
370 spiflashprintstatus(uint8_t status, FILE *out) {
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM.
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parents: 75
diff changeset
371 for (unsigned int i = 0; i < sizeof(flstattbl) / sizeof(flstattbl[0]); i++)
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM.
Daniel O'Connor <darius@dons.net.au>
parents: 75
diff changeset
372 if (status & 1 << i) {
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM.
Daniel O'Connor <darius@dons.net.au>
parents: 75
diff changeset
373 fputs(flstattbl[i], out);
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM.
Daniel O'Connor <darius@dons.net.au>
parents: 75
diff changeset
374 fputs(" ", out);
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM.
Daniel O'Connor <darius@dons.net.au>
parents: 75
diff changeset
375 }
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM.
Daniel O'Connor <darius@dons.net.au>
parents: 75
diff changeset
376 }