stm32temp: spiflash.c annotate

annotate spiflash.c @ 80:1a4573062b37

Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM.

author	Daniel O'Connor <darius@dons.net.au>
date	Sun, 07 Jul 2013 22:49:02 +0930
parents	flash.c@85f16813c730
children	05ba84c7da97

rev	line source
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	1 #include <stdio.h>
8 58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	2 #include <stdint.h>
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	3 #include <string.h>
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	4 #include <stdlib.h>
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	5 #include <assert.h>
8 58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	6
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	7 #include "stm32f10x.h"
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	8 #include "spi.h"
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	9 #include "spiflash.h"
8 58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	10
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	11 #define FL_SELECT() GPIO_ResetBits(GPIOA, GPIO_Pin_4)
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	12 #define FL_DESELECT() GPIO_SetBits(GPIOA, GPIO_Pin_4)
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	13
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	14 const char *flstattbl[] = {
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	15 "BUSY",
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	16 "WEL",
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	17 "BP0",
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	18 "BP1",
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	19 "BP2",
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	20 "BP3",
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	21 "AAI",
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	22 "BPL"
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	23 };
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	24
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	25 #define RW_IDLE 0
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	26 #define RW_RUNNING 1
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	27
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	28 static int writestate = RW_IDLE;
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	29 static int readstate = RW_IDLE;
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	30 #if 0
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	31 void
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	32 spiflashcmd(int argc, char **argv) {
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	33 uint8_t status, tmp, len;
26 74efdb21ae5d Use a 32 bit var to hold address from atoi(). Daniel O'Connor <darius@dons.net.au> parents: 25 diff changeset	34 uint32_t addr;
74efdb21ae5d Use a 32 bit var to hold address from atoi(). Daniel O'Connor <darius@dons.net.au> parents: 25 diff changeset	35
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	36 if (argc == 0) {
75 85f16813c730 Convert \r\n to \n Daniel O'Connor <darius@dons.net.au> parents: 71 diff changeset	37 fputs("No command specified\n", stdout);
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	38 return;
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	39 }
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	40
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	41 if (!strcmp(argv[0], "str")) {
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	42 status = spiflashreadstatus();
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	43 fputs("Status = ", stdout);
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	44 for (unsigned int i = 0; i < sizeof(flstattbl) / sizeof(flstattbl[0]); i++)
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	45 if (status & 1 << i) {
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	46 fputs(flstattbl[i], stdout);
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	47 fputs(" ", stdout);
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	48 }
75 85f16813c730 Convert \r\n to \n Daniel O'Connor <darius@dons.net.au> parents: 71 diff changeset	49 printf("(0x%02x)\n", status);
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	50 } else if (!strcmp(argv[0], "stw")) {
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	51 if (argc != 2) {
75 85f16813c730 Convert \r\n to \n Daniel O'Connor <darius@dons.net.au> parents: 71 diff changeset	52 fputs("Incorrect number of arguments\n", stdout);
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	53 return;
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	54 }
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	55 tmp = atoi(argv[1]);
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	56 spiflashwritestatus(tmp);
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	57 status = spiflashreadstatus();
75 85f16813c730 Convert \r\n to \n Daniel O'Connor <darius@dons.net.au> parents: 71 diff changeset	58 printf("Wrote 0x%02x to status, now 0x%02x\n", tmp, status);
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	59 } else if (!strcmp(argv[0], "er")) {
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	60 if (argc != 2) {
75 85f16813c730 Convert \r\n to \n Daniel O'Connor <darius@dons.net.au> parents: 71 diff changeset	61 fputs("Incorrect number of arguments\n", stdout);
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	62 return;
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	63 }
26 74efdb21ae5d Use a 32 bit var to hold address from atoi(). Daniel O'Connor <darius@dons.net.au> parents: 25 diff changeset	64 addr = atoi(argv[1]);
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	65 spiflash4kerase(addr);
75 85f16813c730 Convert \r\n to \n Daniel O'Connor <darius@dons.net.au> parents: 71 diff changeset	66 printf("Erased 0x%x\n", (unsigned int)addr);
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	67 } else if (!strcmp(argv[0], "rd")) {
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	68 if (argc < 2) {
75 85f16813c730 Convert \r\n to \n Daniel O'Connor <darius@dons.net.au> parents: 71 diff changeset	69 fputs("Incorrect number of arguments\n", stdout);
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	70 return;
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	71 }
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	72
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	73 addr = atoi(argv[1]);
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	74
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	75 if (argc > 2)
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	76 len = atoi(argv[2]);
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	77 else
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	78 len = 16;
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	79
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	80 spiflashstartread(addr);
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	81
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	82 for (uint32_t i = 0; i < len; i++)
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	83 printf("Read 0x%02x from 0x%06x\n", spiflashreadbyte(), (unsigned int)(addr + i));
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	84 spiflashstopread();
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	85
75 85f16813c730 Convert \r\n to \n Daniel O'Connor <darius@dons.net.au> parents: 71 diff changeset	86 fputs("\n", stdout);
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	87 } else if (!strcmp(argv[0], "wr")) {
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	88 if (argc < 2) {
75 85f16813c730 Convert \r\n to \n Daniel O'Connor <darius@dons.net.au> parents: 71 diff changeset	89 fputs("Incorrect number of arguments\n", stdout);
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	90 return;
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	91 }
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	92
26 74efdb21ae5d Use a 32 bit var to hold address from atoi(). Daniel O'Connor <darius@dons.net.au> parents: 25 diff changeset	93 addr = atoi(argv[1]);
74efdb21ae5d Use a 32 bit var to hold address from atoi(). Daniel O'Connor <darius@dons.net.au> parents: 25 diff changeset	94
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	95 if (argc > 2)
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	96 len = atoi(argv[2]);
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	97 else
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	98 len = 16;
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	99
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	100 for (int i = 0; i < 16; i += 2) {
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	101 uint16_t data;
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	102 data = ((i + 1) << 8) \| i;
75 85f16813c730 Convert \r\n to \n Daniel O'Connor <darius@dons.net.au> parents: 71 diff changeset	103 printf("Writing 0x%04x to 0x%06x\n", data, (unsigned int)(addr + i));
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	104
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	105 if (i == 0)
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	106 spiflashstartwrite(addr, data);
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	107 else
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	108 spiflashwriteword(data);
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	109 }
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	110 spiflashstopwrite();
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	111 } else if (!strcmp(argv[0], "id")) {
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	112 printf("Flash ID = 0x%04hx (expect 0xbf41)\n", spiflashreadid());
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	113 } else {
75 85f16813c730 Convert \r\n to \n Daniel O'Connor <darius@dons.net.au> parents: 71 diff changeset	114 fputs("Unknown sub command\n", stdout);
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	115 return;
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	116 }
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	117 }
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	118 #endif
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	119 void
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	120 spiflash4kerase(uint32_t addr) {
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	121 spiflashenablewrite(); /* Enable writing */
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	122
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	123 FL_SELECT(); /* Select device */
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	124
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	125 SPI_WriteByte(FL_4KERASE); /* Send command */
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	126 SPI_WriteByte(addr >> 16); /* Send address */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	127 SPI_WriteByte(addr >> 8);
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	128 SPI_WriteByte(addr);
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	129
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	130 FL_DESELECT();
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	131
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	132 //fputs("4k erase ", stdout);
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	133 spiflashwait();
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	134 }
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	135
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	136 void
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	137 spiflashwait(void) {
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	138 uint8_t cnt;
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	139
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	140 /* Wait for not BUSY */
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	141 for (cnt = 0; (spiflashreadstatus() & FL_BUSY) != 0; cnt++)
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	142 ;
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	143
75 85f16813c730 Convert \r\n to \n Daniel O'Connor <darius@dons.net.au> parents: 71 diff changeset	144 //printf("cnt = %d\n", cnt);
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	145 }
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	146
8 58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	147 uint16_t
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	148 spiflashreadid(void) {
8 58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	149 uint8_t fac, dev;
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	150
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	151 FL_SELECT(); /* Select device */
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	152
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	153 SPI_WriteByte(FL_RDID); /* Send command */
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	154 SPI_WriteByte(0x00); /* Send address cycles (ID data starts at 0) */
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	155 SPI_WriteByte(0x00);
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	156 SPI_WriteByte(0x00);
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	157 fac = SPI_WriteByte(0x00); /* Read ID */
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	158 dev = SPI_WriteByte(0x00);
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	159
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	160 FL_DESELECT(); /* De-select device */
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	161
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	162 return fac << 8 \| dev;
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	163 }
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	164
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	165 void
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	166 spiflashenablewrite(void) {
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	167 FL_SELECT(); /* Select device */
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	168
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	169 SPI_WriteByte(FL_WREN); /* Send command */
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	170
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	171 FL_DESELECT(); /* De-select device */
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	172 }
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	173
8 58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	174 uint8_t
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	175 spiflashreadstatus(void) {
8 58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	176 uint8_t status;
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	177
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	178 FL_SELECT(); /* Select device */
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	179
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	180 SPI_WriteByte(FL_RDSR); /* Send command */
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	181 SPI_WriteByte(0x00); /* Send dummy byte for address cycle */
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	182 status = SPI_WriteByte(0x00); /* Read status */
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	183
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	184 FL_DESELECT(); /* De-select device */
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	185
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	186 return status;
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	187 }
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	188
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	189 void
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	190 spiflashwritestatus(uint8_t status) {
8 58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	191 /* Enable status write */
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	192 FL_SELECT(); /* Select device */
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	193 SPI_WriteByte(FL_EWSR); /* Send command */
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	194 SPI_WriteByte(0x00); /* Send data byte */
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	195 FL_DESELECT();
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	196
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	197 /* Actually write status */
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	198 FL_SELECT(); /* Re-select device for new command */
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	199 SPI_WriteByte(FL_WRSR); /* Send command */
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	200 SPI_WriteByte(status); /* Send data byte */
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	201 FL_DESELECT(); /* De-select device */
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	202 }
58d76cf522ff Split out code into separate files. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	203
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	204 uint8_t
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	205 spiflashread(uint32_t addr) {
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	206 uint8_t data;
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	207
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	208 FL_SELECT(); /* Select device */
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	209
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	210 SPI_WriteByte(FL_READ); /* Send command */
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	211 SPI_WriteByte(addr >> 16); /* Send address */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	212 SPI_WriteByte(addr >> 8);
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	213 SPI_WriteByte(addr);
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	214 data = SPI_WriteByte(0x00); /* Read data */
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	215
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	216 FL_DESELECT(); /* De-select device */
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	217
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	218 return data;
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	219 }
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	220
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	221 void
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	222 spiflashwrite(uint32_t addr, uint8_t data) {
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	223 spiflashwait();
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	224 spiflashenablewrite(); /* Enable writes */
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	225
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	226 FL_SELECT(); /* Select device */
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	227
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	228 SPI_WriteByte(FL_BYTEPROG); /* Send command */
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	229 SPI_WriteByte(addr >> 16); /* Send address */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	230 SPI_WriteByte(addr >> 8);
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	231 SPI_WriteByte(addr);
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	232 SPI_WriteByte(data); /* Write data */
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	233
bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	234 FL_DESELECT(); /* De-select device */
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	235
21 bd8e2cf04034 - Add flash erase, write & read commands (needs more work). Daniel O'Connor <darius@dons.net.au> parents: 8 diff changeset	236 }
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	237
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	238 /*
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	239 * fStream reading looks like so
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	240 *
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	241 */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	242
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	243 void
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	244 spiflashstartread(uint32_t addr) {
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	245 assert(readstate == RW_IDLE);
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	246
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	247 FL_SELECT(); /* Select device */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	248
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	249 SPI_WriteByte(FL_READ); /* Send command */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	250 SPI_WriteByte(addr >> 16); /* Send address */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	251 SPI_WriteByte(addr >> 8);
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	252 SPI_WriteByte(addr);
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	253
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	254 readstate = RW_RUNNING;
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	255 }
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	256
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	257 uint8_t
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	258 spiflashreadbyte(void) {
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	259 assert(readstate == RW_RUNNING);
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	260 return SPI_WriteByte(0x00); /* Read data */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	261 }
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	262
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	263 void
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	264 spiflashstopread(void) {
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	265 assert(readstate == RW_RUNNING);
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	266
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	267 FL_DESELECT();
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	268
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	269 readstate = RW_IDLE;
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	270 }
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	271
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	272 /*
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	273 * Auto increment writing looks like so
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	274 *
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	275 * Enable writing CS, WREN, nCS
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	276 * Send start address & first data word CS, AAI + addr + data, nCS
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	277 * Send subsequent words wait for nBUSY, CS, AAI + data, nCS
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	278 * ...
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	279 * Disable writing CS, WRDI, nCS
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	280 *
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	281 * XXX: EBSY command links SO to flash busy state, I don't think the
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	282 * STM32 could sample it without switching out of SPI mode.
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	283 */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	284 void
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	285 spiflashstartwrite(uint32_t addr, uint16_t data) {
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	286 assert(writestate == RW_IDLE);
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	287
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	288 spiflashenablewrite(); /* Enable writes */
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	289
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	290 FL_SELECT(); /* Select device */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	291
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	292 SPI_WriteByte(FL_AAIWP); /* Send command */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	293 SPI_WriteByte(addr >> 16);
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	294 SPI_WriteByte(addr >> 8);
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	295 SPI_WriteByte(addr & 0xff); /* Send address */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	296
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	297 SPI_WriteByte(data & 0xff); /* Write LSB */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	298 SPI_WriteByte(data >> 8); /* Write MSB */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	299
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	300 FL_DESELECT();
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	301
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	302 writestate = RW_RUNNING;
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	303 }
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	304
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	305 void
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	306 spiflashwriteword(uint16_t data) {
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	307 assert(writestate == RW_RUNNING);
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	308
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	309 //fputs("write word ", stdout);
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	310 spiflashwait(); /* Wait until not busy */
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	311
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	312 FL_SELECT(); /* Select device */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	313
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	314 SPI_WriteByte(FL_AAIWP); /* Send command */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	315 SPI_WriteByte(data & 0xff); /* Write LSB */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	316 SPI_WriteByte(data >> 8); /* Write MSB */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	317
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	318 FL_DESELECT(); /* De-select device */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	319 }
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	320
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	321 void
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	322 spiflashstopwrite(void) {
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	323 assert(writestate == RW_RUNNING);
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	324
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	325 //fputs("flash stop write start ", stdout);
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	326 spiflashwait(); /* Wait until not busy */
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	327
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	328 FL_SELECT(); /* Select device */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	329
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	330 SPI_WriteByte(FL_WRDI); /* Send command */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	331
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	332 FL_DESELECT(); /* Deselect device */
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	333
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	334 //fputs("flash stop write end ", stdout);
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	335 spiflashwait(); /* Wait until not busy */
25 a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	336
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	337 writestate = RW_IDLE;
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	338 }
a9cc07caa801 Add stream read/write commands. Daniel O'Connor <darius@dons.net.au> parents: 21 diff changeset	339
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	340 int
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	341 spiflashreadblock(uint32_t addr, uint32_t len, void *_data) {
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	342 uint8_t *data = _data;
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	343 uint32_t flashcrc, ramcrc;
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	344
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	345 /* Must be a multiple of 4 due to CRC check */
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	346 assert(len % 4 == 0);
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	347
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	348 spiflashstartread(addr);
69 cf9eb08b8b23 CRC a word at a time rather than the whole block (since we are reading/writing a word at a time). Daniel O'Connor <darius@dons.net.au> parents: 67 diff changeset	349 CRC_ResetDR();
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	350 for (int i = len; i > 0; i--) {
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	351 *data = spiflashreadbyte();
69 cf9eb08b8b23 CRC a word at a time rather than the whole block (since we are reading/writing a word at a time). Daniel O'Connor <darius@dons.net.au> parents: 67 diff changeset	352 CRC_CalcCRC(*data);
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	353 data++;
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	354 }
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	355
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	356 flashcrc = spiflashreadbyte();
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	357 flashcrc \|= spiflashreadbyte() << 8;
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	358 flashcrc \|= spiflashreadbyte() << 16;
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	359 flashcrc \|= spiflashreadbyte() << 24;
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	360
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	361 spiflashstopread();
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	362
69 cf9eb08b8b23 CRC a word at a time rather than the whole block (since we are reading/writing a word at a time). Daniel O'Connor <darius@dons.net.au> parents: 67 diff changeset	363 ramcrc = CRC_GetCRC();
cf9eb08b8b23 CRC a word at a time rather than the whole block (since we are reading/writing a word at a time). Daniel O'Connor <darius@dons.net.au> parents: 67 diff changeset	364
75 85f16813c730 Convert \r\n to \n Daniel O'Connor <darius@dons.net.au> parents: 71 diff changeset	365 /* printf("RAM CRC 0x%08x Flash CRC 0x%08x\n", (uint)ramcrc, (uint)flashcrc); */
69 cf9eb08b8b23 CRC a word at a time rather than the whole block (since we are reading/writing a word at a time). Daniel O'Connor <darius@dons.net.au> parents: 67 diff changeset	366 if (ramcrc == flashcrc)
cf9eb08b8b23 CRC a word at a time rather than the whole block (since we are reading/writing a word at a time). Daniel O'Connor <darius@dons.net.au> parents: 67 diff changeset	367 return 1;
cf9eb08b8b23 CRC a word at a time rather than the whole block (since we are reading/writing a word at a time). Daniel O'Connor <darius@dons.net.au> parents: 67 diff changeset	368 else
cf9eb08b8b23 CRC a word at a time rather than the whole block (since we are reading/writing a word at a time). Daniel O'Connor <darius@dons.net.au> parents: 67 diff changeset	369 return 0;
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	370 }
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	371
70 aaf0603d7f88 Add routine to CRC a block of flash. Use it to verify a flash block write. Daniel O'Connor <darius@dons.net.au> parents: 69 diff changeset	372 uint32_t
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	373 spiflashcrcblock(uint32_t addr, uint32_t len) {
70 aaf0603d7f88 Add routine to CRC a block of flash. Use it to verify a flash block write. Daniel O'Connor <darius@dons.net.au> parents: 69 diff changeset	374 assert(len % 4 == 0);
aaf0603d7f88 Add routine to CRC a block of flash. Use it to verify a flash block write. Daniel O'Connor <darius@dons.net.au> parents: 69 diff changeset	375
aaf0603d7f88 Add routine to CRC a block of flash. Use it to verify a flash block write. Daniel O'Connor <darius@dons.net.au> parents: 69 diff changeset	376 CRC_ResetDR();
aaf0603d7f88 Add routine to CRC a block of flash. Use it to verify a flash block write. Daniel O'Connor <darius@dons.net.au> parents: 69 diff changeset	377
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	378 spiflashstartread(addr);
70 aaf0603d7f88 Add routine to CRC a block of flash. Use it to verify a flash block write. Daniel O'Connor <darius@dons.net.au> parents: 69 diff changeset	379 for (int i = len; i > 0; i--)
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	380 CRC_CalcCRC(spiflashreadbyte());
70 aaf0603d7f88 Add routine to CRC a block of flash. Use it to verify a flash block write. Daniel O'Connor <darius@dons.net.au> parents: 69 diff changeset	381
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	382 spiflashstopread();
70 aaf0603d7f88 Add routine to CRC a block of flash. Use it to verify a flash block write. Daniel O'Connor <darius@dons.net.au> parents: 69 diff changeset	383
aaf0603d7f88 Add routine to CRC a block of flash. Use it to verify a flash block write. Daniel O'Connor <darius@dons.net.au> parents: 69 diff changeset	384 return CRC_GetCRC();
aaf0603d7f88 Add routine to CRC a block of flash. Use it to verify a flash block write. Daniel O'Connor <darius@dons.net.au> parents: 69 diff changeset	385 }
aaf0603d7f88 Add routine to CRC a block of flash. Use it to verify a flash block write. Daniel O'Connor <darius@dons.net.au> parents: 69 diff changeset	386
aaf0603d7f88 Add routine to CRC a block of flash. Use it to verify a flash block write. Daniel O'Connor <darius@dons.net.au> parents: 69 diff changeset	387 int
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	388 spiflashwriteblock(uint32_t addr, uint32_t len, void *_data) {
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	389 uint16_t *data = _data;
70 aaf0603d7f88 Add routine to CRC a block of flash. Use it to verify a flash block write. Daniel O'Connor <darius@dons.net.au> parents: 69 diff changeset	390 uint32_t crc, vcrc;
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	391
75 85f16813c730 Convert \r\n to \n Daniel O'Connor <darius@dons.net.au> parents: 71 diff changeset	392 //printf("Writing %u bytes to 0x%06x\n", (uint)len, (uint)addr);
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	393
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	394 /* Ensure data is
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	395 * - 16 bit aligned
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	396 * - a multiple of 32 bits in length (for CRCs, the flash only need 16 bits)
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	397 * - not longer than a sector
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	398 */
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	399 assert(addr % 2 == 0);
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	400 assert(len % 4 == 0);
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	401 assert(len <= 4096);
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	402
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	403 /* Disable write protect */
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	404 spiflashwritestatus(0x00);
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	405
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	406 /* Erase sector */
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	407 spiflash4kerase(addr);
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	408
69 cf9eb08b8b23 CRC a word at a time rather than the whole block (since we are reading/writing a word at a time). Daniel O'Connor <darius@dons.net.au> parents: 67 diff changeset	409 CRC_ResetDR();
cf9eb08b8b23 CRC a word at a time rather than the whole block (since we are reading/writing a word at a time). Daniel O'Connor <darius@dons.net.au> parents: 67 diff changeset	410
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	411 /* Write data */
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	412 for (uint i = 0; i < len / 2; i++) {
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	413 if (i == 0)
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	414 spiflashstartwrite(addr, *data);
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	415 else
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	416 spiflashwriteword(*data);
69 cf9eb08b8b23 CRC a word at a time rather than the whole block (since we are reading/writing a word at a time). Daniel O'Connor <darius@dons.net.au> parents: 67 diff changeset	417 CRC_CalcCRC(*data);
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	418 data++;
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	419 }
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	420
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	421 /* Calculate CRC */
69 cf9eb08b8b23 CRC a word at a time rather than the whole block (since we are reading/writing a word at a time). Daniel O'Connor <darius@dons.net.au> parents: 67 diff changeset	422 crc = CRC_GetCRC();
cf9eb08b8b23 CRC a word at a time rather than the whole block (since we are reading/writing a word at a time). Daniel O'Connor <darius@dons.net.au> parents: 67 diff changeset	423
75 85f16813c730 Convert \r\n to \n Daniel O'Connor <darius@dons.net.au> parents: 71 diff changeset	424 //printf("CRC is 0x%08x\n", (uint)crc);
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	425
5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	426 /* Write CRC */
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	427 spiflashwriteword(crc);
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	428 spiflashwriteword(crc >> 16);
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	429
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	430 spiflashstopwrite();
70 aaf0603d7f88 Add routine to CRC a block of flash. Use it to verify a flash block write. Daniel O'Connor <darius@dons.net.au> parents: 69 diff changeset	431
aaf0603d7f88 Add routine to CRC a block of flash. Use it to verify a flash block write. Daniel O'Connor <darius@dons.net.au> parents: 69 diff changeset	432 /* Read back and check CRC */
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	433 vcrc = spiflashcrcblock(addr, len);
70 aaf0603d7f88 Add routine to CRC a block of flash. Use it to verify a flash block write. Daniel O'Connor <darius@dons.net.au> parents: 69 diff changeset	434 if (vcrc != crc)
aaf0603d7f88 Add routine to CRC a block of flash. Use it to verify a flash block write. Daniel O'Connor <darius@dons.net.au> parents: 69 diff changeset	435 return 1;
aaf0603d7f88 Add routine to CRC a block of flash. Use it to verify a flash block write. Daniel O'Connor <darius@dons.net.au> parents: 69 diff changeset	436 else
aaf0603d7f88 Add routine to CRC a block of flash. Use it to verify a flash block write. Daniel O'Connor <darius@dons.net.au> parents: 69 diff changeset	437 return 0;
27 5c9d2e3d6591 Add flashread/writeblock commands which read/write a block of data to Daniel O'Connor <darius@dons.net.au> parents: 26 diff changeset	438 }
80 1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	439
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	440 void
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	441 spiflashprintstatus(uint8_t status, FILE *out) {
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	442 for (unsigned int i = 0; i < sizeof(flstattbl) / sizeof(flstattbl[0]); i++)
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	443 if (status & 1 << i) {
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	444 fputs(flstattbl[i], out);
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	445 fputs(" ", out);
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	446 }
1a4573062b37 Reshuffle in preparation for being able to have a common API for SPI flash and (emulated) EEPROM. Daniel O'Connor <darius@dons.net.au> parents: 75 diff changeset	447 }

Mercurial > ~darius > hgwebdir.cgi > stm32temp

annotate spiflash.c @ 80:1a4573062b37