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annotate dac.pio @ 25:6070d2e66b4c

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Cascade IRQs from DAC to control so manual & external trigger are the same.
author Daniel O'Connor <darius@dons.net.au>
date Tue, 25 Feb 2025 16:53:32 +1030
parents 9ad0dd5c638c
children e1d8fe3e418a
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1 ;
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2 ; Copyright (c) 2025 Daniel O'Connor
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3 ;
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5 .program dac
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6 .define DAC_IRQ 0
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7 .define DAC_TRIGGER_IRQ 0
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8 .define CTRL_TRIGGER_IRQ 1
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9 ; Need 1 side set pin, the clock
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10 .side_set 1
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12 ; Clock in a 0 byte
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98880b18bcc1 Reset DAC PIO and use force trigger to do manual trigger.
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13 mov pins, null side 0
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14 nop side 1
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15 ; Wait for start trigger and clear IRQ
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16 wait 1 irq DAC_TRIGGER_IRQ side 0
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17 ; Trigger the control SM
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18 irq nowait CTRL_TRIGGER_IRQ side 0
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19 ; Clock DAC and write data from the FIFO
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20 ; DAC clocks data in on the rising clock edge
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21 .wrap_target
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22 out pins 8 side 0
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23 nop side 1
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24 out pins 8 side 0
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25 nop side 1
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26 out pins 8 side 0
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27 nop side 1
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28 out pins 8 side 0
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29 nop side 1
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30 .wrap
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32 % c-sdk {
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33 static inline void dac_program_init(PIO pio, uint sm, uint offset, uint pin, uint clkdiv) {
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34 pio_sm_config c = dac_program_get_default_config(offset);
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36 // Set the OUT base pin to the provided `pin` parameter.
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37 // First 8 pins are data, last is clock
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38 sm_config_set_out_pins(&c, pin, 9);
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39 // Set the pin directions to output at the PIO
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40 pio_sm_set_consecutive_pindirs(pio, sm, pin, 9, true);
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41 // Connect these GPIOs to this PIO block
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42 for (int i = 0; i < 9; i++)
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43 pio_gpio_init(pio, pin + i);
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45 sm_config_set_out_shift(
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46 &c,
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47 true, // Shift-to-right
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48 true, // Autopull enabled
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49 32 // Autopull threshold (bits!)
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50 );
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51
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52 // Configure sideset pin to use for clock
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53 sm_config_set_sideset_pins(&c, pin + 8);
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55 // We only send, so disable the RX FIFO to make the TX FIFO deeper.
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56 sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
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57
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58 sm_config_set_clkdiv(&c, clkdiv);
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60 // Load our configuration, and start the program from the beginning
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61 pio_sm_init(pio, sm, offset, &c);
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62 pio_sm_set_enabled(pio, sm, true);
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63 }
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64 %}