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annotate dac.pio @ 19:2e14ccd1338a

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Set control data after shape data so it is lined up properly.
author Daniel O'Connor <darius@dons.net.au>
date Tue, 25 Feb 2025 14:53:40 +1030
parents f1e44afb41a3
children 9ad0dd5c638c
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1 ;
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2 ; Copyright (c) 2025 Daniel O'Connor
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3 ;
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4
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5 .program dac
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6 .define TRIGGER_IRQ 0
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7 ; Need 1 side set pin, the clock
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8 .side_set 1
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10 ; Clock in a 0 byte
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11 mov pins, null side 0
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12 nop side 1
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13 ; Wait for start trigger and clear IRQ
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14 wait 1 irq 1 side 0
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15 irq clear 1 side 0
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16 ; Clock DAC and write data from the FIFO
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17 ; DAC clocks data in on the rising clock edge
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18 .wrap_target
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19 out pins 8 side 0
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20 nop side 1
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21 out pins 8 side 0
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22 nop side 1
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23 out pins 8 side 0
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24 nop side 1
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25 out pins 8 side 0
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26 nop side 1
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27 .wrap
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29 % c-sdk {
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30 static inline void dac_program_init(PIO pio, uint sm, uint offset, uint pin, uint clkdiv) {
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31 pio_sm_config c = dac_program_get_default_config(offset);
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32
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33 // Set the OUT base pin to the provided `pin` parameter.
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34 // First 8 pins are data, last is clock
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35 sm_config_set_out_pins(&c, pin, 9);
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36 // Set the pin directions to output at the PIO
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37 pio_sm_set_consecutive_pindirs(pio, sm, pin, 9, true);
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38 // Connect these GPIOs to this PIO block
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39 for (int i = 0; i < 9; i++)
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40 pio_gpio_init(pio, pin + i);
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41
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42 sm_config_set_out_shift(
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43 &c,
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44 true, // Shift-to-right
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45 true, // Autopull enabled
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46 32 // Autopull threshold (bits!)
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47 );
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48
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49 // Configure sideset pin to use for clock
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50 sm_config_set_sideset_pins(&c, pin + 8);
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52 // We only send, so disable the RX FIFO to make the TX FIFO deeper.
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53 sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
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54
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55 sm_config_set_clkdiv(&c, clkdiv);
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57 // Load our configuration, and start the program from the beginning
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58 pio_sm_init(pio, sm, offset, &c);
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59 pio_sm_set_enabled(pio, sm, true);
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60 }
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61 %}