Mercurial > ~darius > hgwebdir.cgi > stm32test
annotate lcd.c @ 7:9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Factor out LCD init (needs more work)
author | Daniel O'Connor <darius@dons.net.au> |
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date | Sun, 22 Jan 2012 17:10:51 +1030 |
parents | efa2c22266e3 |
children | 58d76cf522ff |
rev | line source |
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1 /* |
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2 * Example code (I think) |
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3 * ~/projects/STM32Strive/奋斗STM32开发板例程/奋斗STM32开发板例程/奋斗STM32开发板MINI/STM32奋斗版ucOS II V2.86 uCGUI 3.9 DEMO-V2/STM32奋斗版ucOS II V2.86 uCGUI 3.9 DEMO |
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4 * |
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5 * Schematics |
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6 * Main board docs/Strive\ Mini\ STM32\ Schematic.pdf |
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7 * LCD board docs/Strive Mini LCD STM32 Schematic.pdf |
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8 * MCU reference manual docs/CD00171190.pdf |
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9 * MCU Data sheet (pinout) docs/CD00191185.pdf |
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10 * LCD controller data sheet docs/ili9325-v0.35.pdf |
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11 * LCD controller app notes docs/ILI9325AN_V0.22.pdf |
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12 * XXX: not sure what panel is connected |
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13 * |
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14 */ |
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15 /* LCD board MCU |
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16 1 VCC |
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17 2 TC_SCK PA5/SPI1_SCK |
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18 3 GND |
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19 4 TC_CS PB7/SPI1_CS3 |
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20 5 RST PE1 FSMC_NBL1? (unlikely) |
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21 6 TC_DIN PA7/SPI1_MOSI |
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22 7 nOE PD4/FSMC_nOE |
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23 8 TC_DOUT PA6/SPI1_MISO |
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24 9 nWR PD5/FSMC_nWE |
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25 10 TC_INT PB6 |
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26 11 CS PD7/FSMC_NE1/FSMC_NCE2 |
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27 12 NC |
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28 13 RS PD11/FSMC_A16 |
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29 14 NC |
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30 15 D7 PE10/FSMC_D7 |
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31 16 NC |
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32 17 D6 PE9/FSMC_D6 |
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33 18 NC |
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34 19 D3 PD1/FSMC_D3 |
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35 20 D13 PD8/FSMC_D13 |
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36 21 D5 PE8/FSMC_D5 |
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37 22 D12 PE15/FSMC_D12 |
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38 23 D4 PE7/FSMC_D4 |
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39 24 GND |
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40 25 NC |
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41 26 D11 PE14/FSMC_D11 |
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42 27 D2 PD0/FSMC_D2 |
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43 28 D10 PE13/FSMC_D10 |
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44 29 D1 PD15/FSMC_D1 |
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45 30 D9 PE12/FSMC_D9 |
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46 31 D0 PD14/FSMC_D0 |
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47 32 D14 PD9/FSMC_D14 |
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48 33 NC |
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49 34 D8 PE11/FSMC_D8 |
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50 35 NC |
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51 36 NC |
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52 37 NC |
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53 38 LCD_PWM PD13/TIM4_CH2 |
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54 39 NC |
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55 40 D15 PD10/FSMC_D15 |
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56 */ |
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57 |
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58 #include <stdio.h> |
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59 #include "stm32f10x.h" |
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60 #include "lcd.h" |
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61 |
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62 static void LCD_Doinit(void); |
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63 |
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64 #define Bank1_LCD_C ((uint32_t)0x60000000) /* Register Address */ |
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65 #define Bank1_LCD_D ((uint32_t)0x60020000) /* Data Address */ |
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66 |
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67 void |
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68 LCD_WR_Reg(uint16_t index, uint16_t val) { |
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69 *(__IO uint16_t *)(Bank1_LCD_C) = index; |
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70 *(__IO uint16_t *)(Bank1_LCD_D) = val; |
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71 } |
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72 |
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73 uint16_t |
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74 LCD_RD_Reg(uint16_t index) { |
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75 *(__IO uint16_t *)(Bank1_LCD_C) = index; |
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76 return(*(__IO uint16_t *)(Bank1_LCD_D)); |
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77 } |
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78 |
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79 uint16_t |
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80 LCD_RD_Data(int first) { |
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81 uint16_t a = 0; |
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82 if (first) |
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83 a = *(__IO uint16_t *) (Bank1_LCD_D); /* Dummy */ |
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84 a = *(__IO uint16_t *) (Bank1_LCD_D); /* Read */ |
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85 |
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86 return (a); |
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87 } |
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88 |
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89 void |
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90 LCD_WR_StartData(uint16_t x, uint16_t y) { |
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91 LCD_WR_Reg(0x20, x); |
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92 LCD_WR_Reg(0x21, y); |
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93 *(__IO uint16_t *)(Bank1_LCD_C) = 0x22; /* Start GRAM write */ |
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94 } |
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95 |
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96 void |
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97 LCD_WR_Data(uint16_t val) { |
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98 *(__IO uint16_t *)(Bank1_LCD_D) = val; |
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99 } |
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100 |
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101 /* This is a bit rough and ready */ |
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102 void |
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103 Delay(__IO uint32_t nCount) { |
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104 __IO uint32_t i; |
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105 |
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106 for(; nCount != 0; nCount--) |
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107 for (i = 0; i < 3900; i++) |
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108 ; |
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109 } |
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110 |
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111 uint8_t |
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112 SPI_WriteByte(uint8_t out) { |
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113 uint8_t in = 0; |
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114 |
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115 /* Wait until the transmit buffer is empty */ |
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116 while (SPI_I2S_GetFlagStatus(SPI1,SPI_I2S_FLAG_TXE) == RESET) |
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117 ; |
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118 |
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119 /* Send the byte */ |
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120 SPI_I2S_SendData(SPI1, out); |
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121 |
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122 /* Wait until a data is received */ |
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123 while (SPI_I2S_GetFlagStatus(SPI1,SPI_I2S_FLAG_RXNE) == RESET) |
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124 ; |
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125 |
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126 /* Get the received data */ |
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127 in = SPI_I2S_ReceiveData(SPI1); |
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128 |
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129 /* Return the shifted data */ |
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130 return (in); |
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131 } |
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132 |
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133 #define TP_SELECT() GPIO_ResetBits(GPIOB, GPIO_Pin_7) |
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134 #define TP_DESELECT() GPIO_SetBits(GPIOB, GPIO_Pin_7) |
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135 uint16_t |
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136 TPRead(uint8_t type) { |
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137 uint16_t x = 0; |
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138 |
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139 /* Select device */ |
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140 TP_SELECT(); |
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141 |
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142 /* Do conversion */ |
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143 Delay(10); |
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144 SPI_WriteByte(type); |
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145 |
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146 /* Read result */ |
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147 Delay(10); |
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148 x = SPI_WriteByte(0x00); |
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149 x <<= 8; |
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150 x |= SPI_WriteByte(0x00); |
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151 Delay(10); |
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152 |
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153 /* De-select device */ |
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154 TP_DESELECT(); |
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155 |
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156 /* Right justify 12 bit result */ |
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157 x = x >> 3; |
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158 return (x); |
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159 } |
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160 |
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161 #define FL_SELECT() GPIO_ResetBits(GPIOA, GPIO_Pin_4) |
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162 #define FL_DESELECT() GPIO_SetBits(GPIOA, GPIO_Pin_4) |
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163 |
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164 #define FL_READ 0x03 |
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165 #define FL_HSREAD 0x0b |
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166 #define FL_32KERASE 0x52 |
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167 #define FL_64KERASE 0xd8 |
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168 #define FL_CHIPERASE 0x60 |
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169 #define FL_BYTEPROG 0x02 |
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170 #define FL_AAIWP 0xad |
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171 #define FL_RDSR 0x05 |
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172 #define FL_EWSR 0x50 |
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173 #define FL_WRSR 0x01 |
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174 #define FL_WREN 0x06 |
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175 #define FL_WRDI 0x04 |
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176 #define FL_RDID 0x90 |
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177 #define FL_JEDECID 0x9f |
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178 #define FL_EBSY 0x70 |
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179 #define FL_DBSY 0x80 |
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180 |
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181 uint16_t |
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182 FlashReadID(void) { |
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183 uint8_t fac, dev; |
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184 |
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185 FL_SELECT(); /* Select device */ |
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186 |
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187 SPI_WriteByte(FL_RDID); /* Send command */ |
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188 SPI_WriteByte(0x00); /* Send address cycles (ID data starts at 0) */ |
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189 SPI_WriteByte(0x00); |
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190 SPI_WriteByte(0x00); |
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191 fac = SPI_WriteByte(0x00); /* Read ID */ |
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192 dev = SPI_WriteByte(0x00); |
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193 |
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194 FL_DESELECT(); /* De-select device */ |
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195 |
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196 return fac << 8 | dev; |
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197 } |
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198 |
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199 uint8_t |
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200 FlashReadStatus(void) { |
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201 uint8_t status; |
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202 |
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203 FL_SELECT(); /* Select device */ |
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204 |
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205 SPI_WriteByte(FL_RDSR); /* Send command */ |
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206 SPI_WriteByte(0x00); /* Send dummy byte for address cycle */ |
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207 status = SPI_WriteByte(0x00); /* Read status */ |
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208 |
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209 FL_DESELECT(); /* De-select device */ |
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210 |
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211 return status; |
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212 } |
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213 |
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214 void |
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215 FlashWriteStatus(uint8_t status) { |
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216 /* Enable status write */ |
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217 FL_SELECT(); /* Select device */ |
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218 SPI_WriteByte(FL_EWSR); /* Send command */ |
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219 SPI_WriteByte(0x00); /* Send data byte */ |
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220 FL_DESELECT(); |
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221 |
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222 /* Actually write status */ |
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223 FL_SELECT(); /* Re-select device for new command */ |
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224 SPI_WriteByte(FL_WRSR); /* Send command */ |
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225 SPI_WriteByte(status); /* Send data byte */ |
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226 FL_DESELECT(); /* De-select device */ |
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227 } |
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228 |
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229 void |
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230 LCD_init(void) { |
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231 GPIO_InitTypeDef GPIO_InitStructure; |
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232 SPI_InitTypeDef SPI_InitStructure; |
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233 FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; |
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234 FSMC_NORSRAMTimingInitTypeDef p; |
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235 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; |
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236 |
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237 /* Enable FSMC clock */ |
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238 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE); |
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239 |
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240 /* Enable alternate function IO clock */ |
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241 RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); |
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242 |
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243 /* Enable GPIOD clock */ |
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244 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE); |
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245 |
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246 /* Enable GPIOD clock */ |
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247 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE, ENABLE); |
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248 |
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249 /* Configures LCD Control lines (FSMC Pins) in alternate function Push-Pull mode. |
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250 * |
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251 * PD0(D2), PD1(D3), PD4(NOE), PD5(NWE), PD7(NE1/CS), PD8(D13), PD9(D14), |
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252 * PD10(D15), PD11(A16/RS) PD14(D0), PD15(D1) |
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253 */ |
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254 GPIO_InitStructure.GPIO_Pin = (GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_7 | |
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255 GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | |
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256 GPIO_Pin_14 | GPIO_Pin_15); |
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257 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
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258 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; |
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259 GPIO_Init(GPIOD, &GPIO_InitStructure); |
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260 |
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261 /* PE7(D4), PE8(D5), PE9(D6), PE10(D7), PE11(D8), PE12(D9), PE13(D10), |
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262 * PE14(D11), PE15(D12) |
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263 */ |
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264 GPIO_InitStructure.GPIO_Pin = (GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | |
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265 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | |
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266 GPIO_Pin_15); |
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267 GPIO_Init(GPIOE, &GPIO_InitStructure); |
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268 |
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269 /* Configure backlight control (PD13/FSMC_A18 remapped to TIM4_CH2) */ |
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270 /* Enable TIM4 clock */ |
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271 RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE); |
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272 |
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273 /* Enable timer function |
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274 * Note source clock is SYSCLK / 2 = 36MHz |
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275 */ |
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276 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13; |
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277 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
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278 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; |
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279 GPIO_Init(GPIOD, &GPIO_InitStructure); |
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280 |
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281 /* Remap TIM4_CH2 to PD13 */ |
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282 GPIO_PinRemapConfig(GPIO_Remap_TIM4, ENABLE); |
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283 |
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284 /* Reset TIM4 */ |
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285 TIM_DeInit(TIM4); |
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286 |
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287 /* Time Base configuration */ |
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288 TIM_TimeBaseStructure.TIM_Period = 999; |
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289 TIM_TimeBaseStructure.TIM_Prescaler = 0; |
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290 TIM_TimeBaseStructure.TIM_ClockDivision = 0; |
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291 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Down; |
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292 |
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293 TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure); |
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294 |
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295 /* Init to full brightness */ |
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296 lcd_setpwm(1000); |
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297 |
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298 /* Enable timer */ |
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299 TIM_OC2PreloadConfig(TIM4, TIM_OCPreload_Enable); |
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300 TIM_ARRPreloadConfig(TIM4, ENABLE); |
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301 TIM_Cmd(TIM4, ENABLE); |
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302 |
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303 /* Configure reset pin (PE1) as GPIO out PP */ |
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304 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; |
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305 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
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306 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; |
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307 GPIO_Init(GPIOE, &GPIO_InitStructure); |
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308 |
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309 /* Configures the Parallel interface (FSMC) for LCD (Parallel mode) */ |
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310 /* Timing configuration */ |
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311 p.FSMC_AddressSetupTime = 5; |
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312 p.FSMC_AddressHoldTime = 5; |
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313 p.FSMC_DataSetupTime = 5; |
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314 p.FSMC_BusTurnAroundDuration = 0; |
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315 p.FSMC_CLKDivision = 0; |
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316 p.FSMC_DataLatency = 0; |
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317 p.FSMC_AccessMode = FSMC_AccessMode_A; |
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318 |
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319 /* FSMC_Bank1_NORSRAM1 configured as follows: |
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320 - Data/Address MUX = Disable |
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321 - Memory Type = SRAM |
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322 - Data Width = 16bit |
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323 - Write Operation = Enable |
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324 - Extended Mode = Disable |
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325 - Asynchronous Wait = Disable */ |
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326 FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM1; |
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327 FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; |
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328 FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; |
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329 FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; |
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330 FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; |
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331 FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; |
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332 FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; |
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333 FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; |
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334 FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; |
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335 FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; |
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336 FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; |
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337 FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; |
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338 FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; |
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339 FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; |
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340 FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; |
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341 FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); |
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342 |
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343 /* Enable FSMC_Bank1_NORSRAM1 */ |
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344 FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE); |
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345 |
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346 /* Configure touch screen controller |
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347 * |
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348 * Connected to SPI1 which is shared with the AT45DB161D. |
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349 * |
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350 * The touch screen is selected with PB7. |
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351 * The flash chip is selected with PA4. |
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352 */ |
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353 |
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354 /* Enable SPI1 clock */ |
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355 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE); |
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356 |
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357 /* Configure MOSI, MISO and SCLK as alternate function PP */ |
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358 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7; |
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359 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
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360 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; |
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361 GPIO_Init(GPIOA, &GPIO_InitStructure); |
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362 |
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363 /* Configure flash chip select pin (PA4) as GPIO out PP */ |
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364 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4; |
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365 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
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366 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; |
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367 GPIO_Init(GPIOA, &GPIO_InitStructure); |
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368 |
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369 /* Configure touch chip select pin (PB7) as GPIO out PP */ |
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370 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; |
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371 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
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372 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; |
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373 GPIO_Init(GPIOB, &GPIO_InitStructure); |
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374 |
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375 /* De-select touch & flash */ |
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376 GPIO_SetBits(GPIOA, GPIO_Pin_4); |
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377 GPIO_SetBits(GPIOB, GPIO_Pin_7); |
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378 |
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379 /* SPI1 Config */ |
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380 SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; |
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381 SPI_InitStructure.SPI_Mode = SPI_Mode_Master; |
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382 SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; |
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383 SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; |
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384 SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; |
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385 SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; |
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386 SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64; |
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387 SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; |
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388 SPI_InitStructure.SPI_CRCPolynomial = 7; |
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389 SPI_Init(SPI1, &SPI_InitStructure); |
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390 |
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391 /* SPI1 enable */ |
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392 SPI_Cmd(SPI1, ENABLE); |
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393 |
7
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394 LCD_Doinit(); |
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395 } |
5
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396 |
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397 void |
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398 lcd_setpwm(uint16_t val) { |
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399 TIM_OCInitTypeDef TIM_OCInitStructure; |
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400 |
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401 /* Channel 2 configuration in PWM mode */ |
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402 TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; |
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403 TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; |
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404 TIM_OCInitStructure.TIM_Pulse = val; |
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405 TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; |
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406 |
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407 TIM_OC2Init(TIM4, &TIM_OCInitStructure); |
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408 |
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409 } |
7
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410 |
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411 static void |
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412 LCD_Doinit(void) { |
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413 uint16_t id; |
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414 |
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415 /* Initialise LCD panel */ |
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416 |
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417 /* Pull reset pin low */ |
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418 Delay(1); |
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419 GPIO_ResetBits(GPIOE, GPIO_Pin_1); |
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420 Delay(10); |
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421 GPIO_SetBits(GPIOE, GPIO_Pin_1); |
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422 Delay(50); |
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423 |
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424 id = LCD_RD_Reg(0x00); |
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425 if (id != 0x9325) { |
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426 printf("LCD ID doesn't match, expected 0x9325 got 0x%x\r\n", id); |
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427 return; |
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428 } |
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429 printf("LCD ID matches\r\n"); |
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430 |
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431 LCD_WR_Reg(0x00e3, 0x3008); /* Set internal timing (not documented) */ |
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432 LCD_WR_Reg(0x00e7, 0x0012); /* Set internal timing (not documented) */ |
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433 LCD_WR_Reg(0x00ef, 0x1231); /* Set internal timing (not documented) */ |
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434 LCD_WR_Reg(0x0000, 0x0001); /* Start Oscillation */ |
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435 Delay(50); |
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436 LCD_WR_Reg(0x0001, 0x0100); /* set SS (S720 -> S1) */ |
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437 LCD_WR_Reg(0x0002, 0x0700); /* set line inversion (B/C + EOR) */ |
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438 LCD_WR_Reg(0x0004, 0x0000); /* no resizing */ |
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439 LCD_WR_Reg(0x0008, 0x0202); /* set the back porch and front porch (2 lines each) */ |
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440 LCD_WR_Reg(0x0009, 0x0000); /* set non-display area refresh cycle ISC[3:0] */ |
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441 LCD_WR_Reg(0x000a, 0x0000); /* FMARK function */ |
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442 |
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443 LCD_WR_Reg(0x000c, 0x0000); /* RGB ctl - Internal clock, 18bit interface */ |
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444 LCD_WR_Reg(0x000d, 0x0000); /* Frame marker Position */ |
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445 LCD_WR_Reg(0x000f, 0x0000); /* RGB interface polarity */ |
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446 |
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447 /* Power On sequence */ |
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448 LCD_WR_Reg(0x0010, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ |
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449 LCD_WR_Reg(0x0011, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */ |
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450 LCD_WR_Reg(0x0012, 0x0000); /* VREG1OUT voltage */ |
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451 LCD_WR_Reg(0x0013, 0x0000); /* VDV[4:0] for VCOM amplitude */ |
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452 Delay(200); /* Dis-charge capacitor power voltage */ |
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453 LCD_WR_Reg(0x0010, 0x1690); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ |
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454 LCD_WR_Reg(0x0011, 0x0227); /* R11h = 0x0221 at VCI = 3.3V, DC1[2:0], DC0[2:0], VC[2:0] */ |
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455 Delay(50); /* Delay 50ms */ |
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Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
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456 LCD_WR_Reg(0x0012, 0x001c); /* External reference voltage= Vci; */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
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changeset
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457 Delay(50); /* Delay 50ms */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
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458 LCD_WR_Reg(0x0013, 0x1800); /* R13 = 1200 when R12 = 009D; VDV[4:0] for VCOM amplitude */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
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changeset
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459 LCD_WR_Reg(0x0029, 0x001c); /* R29 = 000C when R12 = 009D; VCM[5:0] for VCOMH */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
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460 LCD_WR_Reg(0x002b, 0x000d); /* Frame Rate = 91Hz */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
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461 Delay(50); /* Delay 50ms */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
462 |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
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463 /* Set GRAM area */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
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464 LCD_WR_Reg(0x0050, 0x0000); /* Horizontal GRAM Start Address */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
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465 LCD_WR_Reg(0x0051, 0x00ef); /* Horizontal GRAM End Address */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
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466 LCD_WR_Reg(0x0052, 0x0000); /* Vertical GRAM Start Address */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
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467 LCD_WR_Reg(0x0053, 0x013f); /* Vertical GRAM Start Address */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
468 |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
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469 LCD_WR_Reg(0x0060, 0xa700); /* Gate Scan Line, drive G320 -> G1 */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
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470 LCD_WR_Reg(0x0061, 0x0003); /* VLE & REV */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
471 LCD_WR_Reg(0x006a, 0x0000); /* set scrolling line */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
472 |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
473 /* Partial Display Control */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
474 LCD_WR_Reg(0x0080, 0x0000); /* Image 1 */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
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changeset
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475 LCD_WR_Reg(0x0081, 0x0000); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
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changeset
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476 LCD_WR_Reg(0x0082, 0x0000); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
477 LCD_WR_Reg(0x0083, 0x0000); /* Image 2 */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
478 LCD_WR_Reg(0x0084, 0x0000); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
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changeset
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479 LCD_WR_Reg(0x0085, 0x0000); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
480 |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
481 /* Panel Control */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
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changeset
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482 LCD_WR_Reg(0x0090, 0x0010); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
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changeset
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483 LCD_WR_Reg(0x0092, 0x0000); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
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changeset
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484 LCD_WR_Reg(0x0093, 0x0003); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
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485 LCD_WR_Reg(0x0095, 0x0110); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
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changeset
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486 LCD_WR_Reg(0x0097, 0x0000); /* Undocumented */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
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changeset
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487 LCD_WR_Reg(0x0098, 0x0000); /* Undocumented */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
488 |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
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489 LCD_WR_Reg(0x0007, 0x0133); /* Display on, 262k colour mode (vs 8) */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
490 |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
491 LCD_WR_Reg(0x0003, 0x1030); /* set GRAM write direction and enable BGR, 64K colours, 1 transfers/pixel. */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
492 |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
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493 /* Adjust the Gamma Curve */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
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changeset
|
494 LCD_WR_Reg(0x0030, 0x0006); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
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changeset
|
495 LCD_WR_Reg(0x0031, 0x0101); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
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496 LCD_WR_Reg(0x0032, 0x0003); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
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497 LCD_WR_Reg(0x0035, 0x0106); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
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changeset
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498 LCD_WR_Reg(0x0036, 0x0b02); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
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changeset
|
499 LCD_WR_Reg(0x0037, 0x0302); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
500 LCD_WR_Reg(0x0038, 0x0707); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
501 LCD_WR_Reg(0x0039, 0x0007); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
502 LCD_WR_Reg(0x003c, 0x0600); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
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changeset
|
503 LCD_WR_Reg(0x003d, 0x020b); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
504 |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
505 fputs("Testing\r\n", stdout); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
506 LCD_WR_StartData(0, 0); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
507 LCD_WR_Data(0xa5a5); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
508 LCD_WR_Data(0x5a5a); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
509 LCD_WR_StartData(0, 0); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
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changeset
|
510 if ((id = LCD_RD_Data(1)) != 0xa5a5) |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
511 printf("Expected 0xa5a5 got 0x%04x\r\n", id); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
512 |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
513 if ((id = LCD_RD_Data(0)) != 0x5a5a) |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
514 printf("Expected 0x5a5a got 0x%04x\r\n", id); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
515 |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
516 fputs("Filling\r\n", stdout); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
517 /* Fill panel */ |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
518 LCD_WR_StartData(0, 0); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
519 |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
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diff
changeset
|
520 #define RGB24_565(R, G, B) (((((R) >> 3) & 0x1f) << 11) | ((((G) >> 2) & 0x3f) << 5) | (((B) >> 3) & 0x1f)) |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
521 |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
522 for (int x = 0; x < 320; x++) { |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
523 for (int y = 0; y < 240; y++) { |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
524 if (((x / 5) % 3) == 0) |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
525 LCD_WR_Data(RGB24_565(255, 0, 0)); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
526 else if (((x / 5) % 3) == 1) |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
527 LCD_WR_Data(RGB24_565(0, 255, 0)); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
528 else |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
529 LCD_WR_Data(RGB24_565(0, 0, 255)); |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
530 } |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
531 } |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
532 |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
533 } |
9404b9869c27
Make the LCD panel work (timings, GPIOE clock needs to be on, etc)
Daniel O'Connor <darius@dons.net.au>
parents:
5
diff
changeset
|
534 |