Mercurial > ~darius > hgwebdir.cgi > stm32temp
diff libs/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/readme.txt @ 0:c59513fd84fb
Initial commit of STM32 test code.
author | Daniel O'Connor <darius@dons.net.au> |
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date | Mon, 03 Oct 2011 21:19:15 +1030 |
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/libs/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/readme.txt Mon Oct 03 21:19:15 2011 +1030 @@ -0,0 +1,101 @@ +/** + @page TIM1_DMABURST TIM1 DMA Burst transfer example + + @verbatim + ******************** (C) COPYRIGHT 2011 STMicroelectronics ******************* + * @file TIM/DMABurst/readme.txt + * @author MCD Application Team + * @version V3.5.0 + * @date 08-April-2011 + * @brief Description of the TIM1 DMA Burst transfer example. + ****************************************************************************** + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to update the TIM1 channel1 period and the duty cycle +using the TIM1 DMA burst feature. + +Every update DMA request, the DMA will do 3 transfers of half words into Timer +registers beginning from ARR register. +On the DMA update request, 0x0FFF will be transferred into ARR, 0x0000 +will be transferred into RCR, 0x0555 will be transferred into CCR1. + +The TIM1CLK frequency is set to SystemCoreClock (Hz), to get TIM1 counter +clock at 24 MHz the Prescaler is computed as following: + - Prescaler = (TIM1CLK / TIM1 counter clock) - 1 +SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density +and Connectivity line devices and to 24 MHz for Value line devices. + +The TIM1 period is 5.8 KHz: TIM1 Frequency = TIM1 counter clock/(ARR + 1) + = 24 MHz / 4096 = 5.8 KHz +The TIM1 CCR1 register value is equal to 0x555, so the TIM1 Channel 1 generates a +PWM signal with a frequency equal to 5.8 KHz and a duty cycle equal to 33.33%: +TIM1 Channel1 duty cycle = (TIM1_CCR1/ TIM1_ARR + 1)* 100 = 33.33% + +The PWM waveform can be displayed using an oscilloscope. + +@note No need of RCR update, but we should do it because of the ARR and CCR1 + mapping. + + +@par Directory contents + + - TIM/DMABurst/stm32f10x_conf.h Library Configuration file + - TIM/DMABurst/stm32f10x_it.c Interrupt handlers + - TIM/DMABurst/stm32f10x_it.h Interrupt handlers header file + - TIM/DMABurst/main.c Main program + - TIM/DMABurst/system_stm32f10x.c STM32F10x system source file + +@par Hardware and Software environment + + - This example runs on STM32F10x Connectivity line, High-Density, High-Density + Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density + and Low-Density Value line Devices. + + - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density + Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), + STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) + evaluation boards and can be easily tailored to any other supported device + and development board. + + - STM32100E-EVAL, STM32100B-EVAL, STM3210C-EVAL, STM3210E-EVAL, STM32100E-EVAL and STM3210B-EVAL Set-up + - Connect the following pins to an oscilloscope to monitor the different + waveforms: + - TIM1 CH1 (PA.08) + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F10x_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + +@note + - Low-density Value line devices are STM32F100xx microcontrollers where the + Flash memory density ranges between 16 and 32 Kbytes. + - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx + microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. + - Medium-density Value line devices are STM32F100xx microcontrollers where + the Flash memory density ranges between 64 and 128 Kbytes. + - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx + microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. + - High-density Value line devices are STM32F100xx microcontrollers where + the Flash memory density ranges between 256 and 512 Kbytes. + - High-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 256 and 512 Kbytes. + - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 512 and 1024 Kbytes. + - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. + + * <h3><center>© COPYRIGHT 2011 STMicroelectronics</center></h3> + */