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Initial commit of STM32 test code.
author Daniel O'Connor <darius@dons.net.au>
date Mon, 03 Oct 2011 21:19:15 +1030
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1 /**
2 @page TIM1_DMABURST TIM1 DMA Burst transfer example
3
4 @verbatim
5 ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
6 * @file TIM/DMABurst/readme.txt
7 * @author MCD Application Team
8 * @version V3.5.0
9 * @date 08-April-2011
10 * @brief Description of the TIM1 DMA Burst transfer example.
11 ******************************************************************************
12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 ******************************************************************************
19 @endverbatim
20
21 @par Example Description
22
23 This example shows how to update the TIM1 channel1 period and the duty cycle
24 using the TIM1 DMA burst feature.
25
26 Every update DMA request, the DMA will do 3 transfers of half words into Timer
27 registers beginning from ARR register.
28 On the DMA update request, 0x0FFF will be transferred into ARR, 0x0000
29 will be transferred into RCR, 0x0555 will be transferred into CCR1.
30
31 The TIM1CLK frequency is set to SystemCoreClock (Hz), to get TIM1 counter
32 clock at 24 MHz the Prescaler is computed as following:
33 - Prescaler = (TIM1CLK / TIM1 counter clock) - 1
34 SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
35 and Connectivity line devices and to 24 MHz for Value line devices.
36
37 The TIM1 period is 5.8 KHz: TIM1 Frequency = TIM1 counter clock/(ARR + 1)
38 = 24 MHz / 4096 = 5.8 KHz
39 The TIM1 CCR1 register value is equal to 0x555, so the TIM1 Channel 1 generates a
40 PWM signal with a frequency equal to 5.8 KHz and a duty cycle equal to 33.33%:
41 TIM1 Channel1 duty cycle = (TIM1_CCR1/ TIM1_ARR + 1)* 100 = 33.33%
42
43 The PWM waveform can be displayed using an oscilloscope.
44
45 @note No need of RCR update, but we should do it because of the ARR and CCR1
46 mapping.
47
48
49 @par Directory contents
50
51 - TIM/DMABurst/stm32f10x_conf.h Library Configuration file
52 - TIM/DMABurst/stm32f10x_it.c Interrupt handlers
53 - TIM/DMABurst/stm32f10x_it.h Interrupt handlers header file
54 - TIM/DMABurst/main.c Main program
55 - TIM/DMABurst/system_stm32f10x.c STM32F10x system source file
56
57 @par Hardware and Software environment
58
59 - This example runs on STM32F10x Connectivity line, High-Density, High-Density
60 Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density
61 and Low-Density Value line Devices.
62
63 - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
64 Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line),
65 STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density)
66 evaluation boards and can be easily tailored to any other supported device
67 and development board.
68
69 - STM32100E-EVAL, STM32100B-EVAL, STM3210C-EVAL, STM3210E-EVAL, STM32100E-EVAL and STM3210B-EVAL Set-up
70 - Connect the following pins to an oscilloscope to monitor the different
71 waveforms:
72 - TIM1 CH1 (PA.08)
73
74 @par How to use it ?
75
76 In order to make the program work, you must do the following :
77 - Copy all source files from this example folder to the template folder under
78 Project\STM32F10x_StdPeriph_Template
79 - Open your preferred toolchain
80 - Rebuild all files and load your image into target memory
81 - Run the example
82
83 @note
84 - Low-density Value line devices are STM32F100xx microcontrollers where the
85 Flash memory density ranges between 16 and 32 Kbytes.
86 - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
87 microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
88 - Medium-density Value line devices are STM32F100xx microcontrollers where
89 the Flash memory density ranges between 64 and 128 Kbytes.
90 - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
91 microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
92 - High-density Value line devices are STM32F100xx microcontrollers where
93 the Flash memory density ranges between 256 and 512 Kbytes.
94 - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
95 the Flash memory density ranges between 256 and 512 Kbytes.
96 - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
97 the Flash memory density ranges between 512 and 1024 Kbytes.
98 - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
99
100 * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
101 */