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comparison sd.c @ 55:b21db2b47a27

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Enable DMA mode by initing DMA channel and enabling IRQ handler.
author Daniel O'Connor <darius@dons.net.au>
date Sun, 07 Apr 2013 22:34:05 +0930
parents 79c7892d07b3
children f0563086040d
comparison
equal deleted inserted replaced
54:79c7892d07b3 55:b21db2b47a27
360 #endif 360 #endif
361 } 361 }
362 362
363 void 363 void
364 SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize) { 364 SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize) {
365 printf("SD_LowLevel_DMA_RxConfig unimplemented\n"); 365 DMA_InitTypeDef DMA_InitStructure;
366 abort(); 366
367 DMA_ClearFlag(DMA2_FLAG_TC4 | DMA2_FLAG_TE4 | DMA2_FLAG_HT4 | DMA2_FLAG_GL4);
368
369 /* DMA2 Channel4 disable */
370 DMA_Cmd(DMA2_Channel4, DISABLE);
371
372 /* DMA2 Channel4 Config */
373 DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)0x40018080;
374 DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)BufferDST;
375 DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
376 DMA_InitStructure.DMA_BufferSize = BufferSize / 4;
377 DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
378 DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
379 DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
380 DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
381 DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
382 DMA_InitStructure.DMA_Priority = DMA_Priority_High;
383 DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
384 DMA_Init(DMA2_Channel4, &DMA_InitStructure);
385
386 /* DMA2 Channel4 enable */
387 DMA_Cmd(DMA2_Channel4, ENABLE);
367 } 388 }
368 389
369 void 390 void
370 SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize) { 391 SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize) {
371 printf("SD_LowLevel_DMA_TxConfig unimplemented\n"); 392 DMA_InitTypeDef DMA_InitStructure;
372 abort(); 393
394 DMA_ClearFlag(DMA2_FLAG_TC4 | DMA2_FLAG_TE4 | DMA2_FLAG_HT4 | DMA2_FLAG_GL4);
395
396 /* DMA2 Channel4 disable */
397 DMA_Cmd(DMA2_Channel4, DISABLE);
398
399 /* DMA2 Channel4 Config */
400 DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)0x40018080;
401 DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)BufferSRC;
402 DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
403 DMA_InitStructure.DMA_BufferSize = BufferSize / 4;
404 DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
405 DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
406 DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
407 DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
408 DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
409 DMA_InitStructure.DMA_Priority = DMA_Priority_High;
410 DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
411 DMA_Init(DMA2_Channel4, &DMA_InitStructure);
412
413 /* DMA2 Channel4 enable */
414 DMA_Cmd(DMA2_Channel4, ENABLE);
373 } 415 }
374 416
375 uint32_t SD_DMAEndOfTransferStatus(void) { 417 uint32_t SD_DMAEndOfTransferStatus(void) {
376 return (uint32_t)DMA_GetFlagStatus(DMA2_FLAG_TC4); 418 return (uint32_t)DMA_GetFlagStatus(DMA2_FLAG_TC4);
377 } 419 }
476 printf("0x%04lx: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", i, 518 printf("0x%04lx: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", i,
477 buf[i + 0], buf[i + 1], buf[i + 2], buf[i + 3], buf[i + 4], buf[i + 5], buf[i + 6], buf[i + 7], 519 buf[i + 0], buf[i + 1], buf[i + 2], buf[i + 3], buf[i + 4], buf[i + 5], buf[i + 6], buf[i + 7],
478 buf[i + 8], buf[i + 9], buf[i + 10], buf[i + 11], buf[i + 12], buf[i + 13], buf[i + 14], buf[i + 15]); 520 buf[i + 8], buf[i + 9], buf[i + 10], buf[i + 11], buf[i + 12], buf[i + 13], buf[i + 14], buf[i + 15]);
479 } 521 }
480 } 522 }
523
524 void SDIO_IRQHandler(void) {
525 /* Process All SDIO Interrupt Sources */
526 SD_ProcessIRQSrc();
527 }
528