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Initial commit of STM32 test code.
author Daniel O'Connor <darius@dons.net.au>
date Mon, 03 Oct 2011 21:19:15 +1030
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1 /**
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2 @page DMA_FSMC DMA FSMC example
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3
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4 @verbatim
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5 ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
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6 * @file DMA/FSMC/readme.txt
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7 * @author MCD Application Team
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8 * @version V3.5.0
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9 * @date 08-April-2011
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10 * @brief Description of the DMA FSMC example.
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11 ******************************************************************************
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12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 ******************************************************************************
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19 @endverbatim
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20
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21 @par Example Description
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22
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23 This example provides a description of how to use two DMA channels to transfer
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24 a word data buffer from Flash memory to external SRAM memory and to recuperate
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25 the written data from external SRAM to be stored in internal SRAM.
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26
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27 DMA2 Channel5 is configured to transfer, word by word, the contents of a 32-word data
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28 buffer stored in Flash memory to the external SRAM memory interfaced by FSMC.
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29 The start of transfer is triggered by software. DMA2 Channel5 memory-to-memory
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30 transfer is enabled.
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31 Source and destination address incrementing is also enabled. The transfer is started
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32 by setting the Channel enable bit for DMA2 Channel5. A polling on the Transfer Complete
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33 flag is done to check the end of transfer. The DMA2 Channel5 Transfer complete flag
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34 is then cleared.
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35
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36 DMA1 Channel3 is configured to transfer, byte by byte, the contents of the first
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37 128Bytes of external SRAM to the internal SRAM memory. The start of transfer is
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38 triggered by software. DMA1 Channel3 memory-to-memory transfer is enabled.
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39 Source and destination address incrementing is also enabled. The transfer is started
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40 by setting the Channel enable bit for DMA1 Channel3. A polling on the Transfer Complete
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41 flag is done to check the end of transfer.
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42
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43 A comparison between the source and destination buffers is done to check that all data
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44 have been correctly transferred.
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45
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46
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47 @par Directory contents
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48
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49 - DMA/FSMC/stm32f10x_conf.h Library Configuration file
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50 - DMA/FSMC/stm32f10x_it.c Interrupt handlers
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51 - DMA/FSMC/stm32f10x_it.h Interrupt handlers header file
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52 - DMA/FSMC/main.c Main program
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53 - DMA/FSMC/system_stm32f10x.c STM32F10x system source file
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54
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55 @par Hardware and Software environment
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56
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57 - This example runs only on STM32F10x High-Density, High-Density Value line
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58 and XL-Density Devices.
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59
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60 - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
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61 Value line) and STM3210E-EVAL (High-Density and XL-Density) evaluation boards
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62 and can be easily tailored to any other supported device and development board.
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63
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64
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65 @par How to use it ?
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66
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67 In order to make the program work, you must do the following :
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68 - Copy all source files from this example folder to the template folder under
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69 Project\STM32F10x_StdPeriph_Template
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70 - Open your preferred toolchain
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71 - Rebuild all files and load your image into target memory
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72 - Run the example
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73
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74 @note
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75 - Low-density Value line devices are STM32F100xx microcontrollers where the
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76 Flash memory density ranges between 16 and 32 Kbytes.
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77 - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
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78 microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
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79 - Medium-density Value line devices are STM32F100xx microcontrollers where
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80 the Flash memory density ranges between 64 and 128 Kbytes.
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81 - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
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82 microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
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83 - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
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84 the Flash memory density ranges between 256 and 512 Kbytes.
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85 - High-density Value line devices are STM32F100xx microcontrollers where
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86 the Flash memory density ranges between 256 and 512 Kbytes.
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87 - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
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88 the Flash memory density ranges between 512 and 1024 Kbytes.
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89 - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
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90
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91 * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
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92 */