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annotate libs/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c @ 0:c59513fd84fb
Initial commit of STM32 test code.
author | Daniel O'Connor <darius@dons.net.au> |
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date | Mon, 03 Oct 2011 21:19:15 +1030 |
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1 /** |
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2 ****************************************************************************** |
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3 * @file stm32f10x_rcc.c |
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4 * @author MCD Application Team |
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5 * @version V3.5.0 |
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6 * @date 11-March-2011 |
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7 * @brief This file provides all the RCC firmware functions. |
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8 ****************************************************************************** |
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9 * @attention |
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10 * |
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11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
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12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
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13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
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14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
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15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
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16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
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17 * |
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18 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
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19 ****************************************************************************** |
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20 */ |
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21 |
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22 /* Includes ------------------------------------------------------------------*/ |
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23 #include "stm32f10x_rcc.h" |
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24 |
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25 /** @addtogroup STM32F10x_StdPeriph_Driver |
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26 * @{ |
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27 */ |
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28 |
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29 /** @defgroup RCC |
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30 * @brief RCC driver modules |
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31 * @{ |
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32 */ |
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33 |
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34 /** @defgroup RCC_Private_TypesDefinitions |
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35 * @{ |
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36 */ |
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37 |
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38 /** |
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39 * @} |
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40 */ |
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41 |
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42 /** @defgroup RCC_Private_Defines |
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43 * @{ |
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44 */ |
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45 |
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46 /* ------------ RCC registers bit address in the alias region ----------- */ |
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47 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) |
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48 |
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49 /* --- CR Register ---*/ |
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50 |
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51 /* Alias word address of HSION bit */ |
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52 #define CR_OFFSET (RCC_OFFSET + 0x00) |
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53 #define HSION_BitNumber 0x00 |
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54 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) |
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55 |
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56 /* Alias word address of PLLON bit */ |
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57 #define PLLON_BitNumber 0x18 |
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58 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) |
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59 |
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60 #ifdef STM32F10X_CL |
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61 /* Alias word address of PLL2ON bit */ |
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62 #define PLL2ON_BitNumber 0x1A |
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63 #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4)) |
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64 |
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65 /* Alias word address of PLL3ON bit */ |
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66 #define PLL3ON_BitNumber 0x1C |
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67 #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4)) |
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68 #endif /* STM32F10X_CL */ |
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69 |
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70 /* Alias word address of CSSON bit */ |
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71 #define CSSON_BitNumber 0x13 |
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72 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) |
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73 |
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74 /* --- CFGR Register ---*/ |
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75 |
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76 /* Alias word address of USBPRE bit */ |
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77 #define CFGR_OFFSET (RCC_OFFSET + 0x04) |
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78 |
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79 #ifndef STM32F10X_CL |
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80 #define USBPRE_BitNumber 0x16 |
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81 #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) |
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82 #else |
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83 #define OTGFSPRE_BitNumber 0x16 |
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84 #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4)) |
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85 #endif /* STM32F10X_CL */ |
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86 |
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87 /* --- BDCR Register ---*/ |
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88 |
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89 /* Alias word address of RTCEN bit */ |
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90 #define BDCR_OFFSET (RCC_OFFSET + 0x20) |
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91 #define RTCEN_BitNumber 0x0F |
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92 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) |
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93 |
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94 /* Alias word address of BDRST bit */ |
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95 #define BDRST_BitNumber 0x10 |
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96 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) |
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97 |
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98 /* --- CSR Register ---*/ |
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99 |
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100 /* Alias word address of LSION bit */ |
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101 #define CSR_OFFSET (RCC_OFFSET + 0x24) |
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102 #define LSION_BitNumber 0x00 |
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103 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) |
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104 |
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105 #ifdef STM32F10X_CL |
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106 /* --- CFGR2 Register ---*/ |
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107 |
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108 /* Alias word address of I2S2SRC bit */ |
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109 #define CFGR2_OFFSET (RCC_OFFSET + 0x2C) |
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110 #define I2S2SRC_BitNumber 0x11 |
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111 #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4)) |
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112 |
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113 /* Alias word address of I2S3SRC bit */ |
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114 #define I2S3SRC_BitNumber 0x12 |
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115 #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4)) |
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116 #endif /* STM32F10X_CL */ |
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117 |
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118 /* ---------------------- RCC registers bit mask ------------------------ */ |
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119 |
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120 /* CR register bit mask */ |
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121 #define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) |
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122 #define CR_HSEBYP_Set ((uint32_t)0x00040000) |
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123 #define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) |
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124 #define CR_HSEON_Set ((uint32_t)0x00010000) |
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125 #define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) |
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126 |
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127 /* CFGR register bit mask */ |
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128 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) |
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129 #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF) |
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130 #else |
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131 #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) |
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132 #endif /* STM32F10X_CL */ |
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133 |
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134 #define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) |
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135 #define CFGR_PLLSRC_Mask ((uint32_t)0x00010000) |
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136 #define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) |
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137 #define CFGR_SWS_Mask ((uint32_t)0x0000000C) |
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138 #define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) |
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139 #define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) |
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140 #define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) |
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141 #define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) |
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142 #define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) |
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143 #define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) |
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144 #define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) |
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145 #define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) |
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146 #define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) |
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147 |
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148 /* CSR register bit mask */ |
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149 #define CSR_RMVF_Set ((uint32_t)0x01000000) |
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150 |
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151 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) |
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152 /* CFGR2 register bit mask */ |
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153 #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) |
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154 #define CFGR2_PREDIV1 ((uint32_t)0x0000000F) |
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155 #endif |
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156 #ifdef STM32F10X_CL |
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157 #define CFGR2_PREDIV2 ((uint32_t)0x000000F0) |
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158 #define CFGR2_PLL2MUL ((uint32_t)0x00000F00) |
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159 #define CFGR2_PLL3MUL ((uint32_t)0x0000F000) |
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160 #endif /* STM32F10X_CL */ |
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161 |
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162 /* RCC Flag Mask */ |
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163 #define FLAG_Mask ((uint8_t)0x1F) |
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164 |
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165 /* CIR register byte 2 (Bits[15:8]) base address */ |
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166 #define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) |
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167 |
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168 /* CIR register byte 3 (Bits[23:16]) base address */ |
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169 #define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) |
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170 |
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171 /* CFGR register byte 4 (Bits[31:24]) base address */ |
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172 #define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) |
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173 |
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174 /* BDCR register base address */ |
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175 #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) |
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176 |
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177 /** |
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178 * @} |
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179 */ |
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180 |
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181 /** @defgroup RCC_Private_Macros |
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182 * @{ |
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183 */ |
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184 |
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185 /** |
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186 * @} |
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187 */ |
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188 |
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189 /** @defgroup RCC_Private_Variables |
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190 * @{ |
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191 */ |
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192 |
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193 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; |
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194 static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; |
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195 |
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196 /** |
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197 * @} |
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198 */ |
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199 |
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200 /** @defgroup RCC_Private_FunctionPrototypes |
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201 * @{ |
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202 */ |
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203 |
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204 /** |
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205 * @} |
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206 */ |
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207 |
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208 /** @defgroup RCC_Private_Functions |
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209 * @{ |
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210 */ |
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211 |
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212 /** |
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213 * @brief Resets the RCC clock configuration to the default reset state. |
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214 * @param None |
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215 * @retval None |
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216 */ |
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217 void RCC_DeInit(void) |
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218 { |
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219 /* Set HSION bit */ |
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220 RCC->CR |= (uint32_t)0x00000001; |
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221 |
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222 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ |
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223 #ifndef STM32F10X_CL |
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224 RCC->CFGR &= (uint32_t)0xF8FF0000; |
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225 #else |
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226 RCC->CFGR &= (uint32_t)0xF0FF0000; |
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227 #endif /* STM32F10X_CL */ |
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228 |
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229 /* Reset HSEON, CSSON and PLLON bits */ |
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230 RCC->CR &= (uint32_t)0xFEF6FFFF; |
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231 |
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232 /* Reset HSEBYP bit */ |
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233 RCC->CR &= (uint32_t)0xFFFBFFFF; |
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234 |
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235 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ |
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236 RCC->CFGR &= (uint32_t)0xFF80FFFF; |
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237 |
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238 #ifdef STM32F10X_CL |
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239 /* Reset PLL2ON and PLL3ON bits */ |
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240 RCC->CR &= (uint32_t)0xEBFFFFFF; |
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241 |
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242 /* Disable all interrupts and clear pending bits */ |
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243 RCC->CIR = 0x00FF0000; |
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244 |
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245 /* Reset CFGR2 register */ |
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246 RCC->CFGR2 = 0x00000000; |
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247 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
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248 /* Disable all interrupts and clear pending bits */ |
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249 RCC->CIR = 0x009F0000; |
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250 |
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251 /* Reset CFGR2 register */ |
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252 RCC->CFGR2 = 0x00000000; |
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253 #else |
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254 /* Disable all interrupts and clear pending bits */ |
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255 RCC->CIR = 0x009F0000; |
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256 #endif /* STM32F10X_CL */ |
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257 |
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258 } |
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259 |
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260 /** |
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261 * @brief Configures the External High Speed oscillator (HSE). |
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262 * @note HSE can not be stopped if it is used directly or through the PLL as system clock. |
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263 * @param RCC_HSE: specifies the new state of the HSE. |
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264 * This parameter can be one of the following values: |
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265 * @arg RCC_HSE_OFF: HSE oscillator OFF |
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266 * @arg RCC_HSE_ON: HSE oscillator ON |
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267 * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock |
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268 * @retval None |
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269 */ |
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270 void RCC_HSEConfig(uint32_t RCC_HSE) |
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271 { |
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272 /* Check the parameters */ |
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273 assert_param(IS_RCC_HSE(RCC_HSE)); |
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274 /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ |
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275 /* Reset HSEON bit */ |
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276 RCC->CR &= CR_HSEON_Reset; |
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277 /* Reset HSEBYP bit */ |
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278 RCC->CR &= CR_HSEBYP_Reset; |
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279 /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ |
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280 switch(RCC_HSE) |
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281 { |
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282 case RCC_HSE_ON: |
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283 /* Set HSEON bit */ |
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284 RCC->CR |= CR_HSEON_Set; |
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285 break; |
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286 |
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287 case RCC_HSE_Bypass: |
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288 /* Set HSEBYP and HSEON bits */ |
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289 RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; |
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290 break; |
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291 |
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292 default: |
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293 break; |
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294 } |
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295 } |
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296 |
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297 /** |
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298 * @brief Waits for HSE start-up. |
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299 * @param None |
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300 * @retval An ErrorStatus enumuration value: |
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301 * - SUCCESS: HSE oscillator is stable and ready to use |
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302 * - ERROR: HSE oscillator not yet ready |
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303 */ |
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304 ErrorStatus RCC_WaitForHSEStartUp(void) |
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305 { |
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306 __IO uint32_t StartUpCounter = 0; |
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307 ErrorStatus status = ERROR; |
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308 FlagStatus HSEStatus = RESET; |
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309 |
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310 /* Wait till HSE is ready and if Time out is reached exit */ |
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311 do |
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312 { |
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313 HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); |
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314 StartUpCounter++; |
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315 } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); |
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316 |
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317 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) |
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318 { |
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319 status = SUCCESS; |
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320 } |
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321 else |
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322 { |
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323 status = ERROR; |
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324 } |
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325 return (status); |
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326 } |
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327 |
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328 /** |
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329 * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. |
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330 * @param HSICalibrationValue: specifies the calibration trimming value. |
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331 * This parameter must be a number between 0 and 0x1F. |
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332 * @retval None |
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333 */ |
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334 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) |
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335 { |
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336 uint32_t tmpreg = 0; |
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337 /* Check the parameters */ |
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338 assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); |
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339 tmpreg = RCC->CR; |
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340 /* Clear HSITRIM[4:0] bits */ |
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341 tmpreg &= CR_HSITRIM_Mask; |
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342 /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ |
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343 tmpreg |= (uint32_t)HSICalibrationValue << 3; |
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344 /* Store the new value */ |
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345 RCC->CR = tmpreg; |
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346 } |
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347 |
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348 /** |
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349 * @brief Enables or disables the Internal High Speed oscillator (HSI). |
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350 * @note HSI can not be stopped if it is used directly or through the PLL as system clock. |
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351 * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE. |
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352 * @retval None |
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353 */ |
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354 void RCC_HSICmd(FunctionalState NewState) |
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355 { |
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356 /* Check the parameters */ |
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357 assert_param(IS_FUNCTIONAL_STATE(NewState)); |
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358 *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; |
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359 } |
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360 |
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361 /** |
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362 * @brief Configures the PLL clock source and multiplication factor. |
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363 * @note This function must be used only when the PLL is disabled. |
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364 * @param RCC_PLLSource: specifies the PLL entry clock source. |
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365 * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, |
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366 * this parameter can be one of the following values: |
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367 * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry |
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368 * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry |
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369 * For @b other_STM32_devices, this parameter can be one of the following values: |
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370 * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry |
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371 * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry |
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372 * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry |
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373 * @param RCC_PLLMul: specifies the PLL multiplication factor. |
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374 * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5} |
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375 * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16] |
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376 * @retval None |
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377 */ |
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378 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) |
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379 { |
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380 uint32_t tmpreg = 0; |
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381 |
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382 /* Check the parameters */ |
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383 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); |
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384 assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); |
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385 |
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386 tmpreg = RCC->CFGR; |
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387 /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ |
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388 tmpreg &= CFGR_PLL_Mask; |
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389 /* Set the PLL configuration bits */ |
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390 tmpreg |= RCC_PLLSource | RCC_PLLMul; |
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parents:
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391 /* Store the new value */ |
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392 RCC->CFGR = tmpreg; |
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393 } |
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394 |
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395 /** |
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396 * @brief Enables or disables the PLL. |
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397 * @note The PLL can not be disabled if it is used as system clock. |
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398 * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE. |
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399 * @retval None |
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400 */ |
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401 void RCC_PLLCmd(FunctionalState NewState) |
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402 { |
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403 /* Check the parameters */ |
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404 assert_param(IS_FUNCTIONAL_STATE(NewState)); |
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405 |
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406 *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; |
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407 } |
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408 |
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409 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) |
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410 /** |
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411 * @brief Configures the PREDIV1 division factor. |
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412 * @note |
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413 * - This function must be used only when the PLL is disabled. |
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414 * - This function applies only to STM32 Connectivity line and Value line |
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415 * devices. |
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416 * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source. |
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417 * This parameter can be one of the following values: |
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418 * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock |
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419 * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock |
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420 * @note |
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421 * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE |
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422 * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. |
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423 * This parameter can be RCC_PREDIV1_Divx where x:[1,16] |
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424 * @retval None |
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425 */ |
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426 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) |
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427 { |
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428 uint32_t tmpreg = 0; |
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429 |
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430 /* Check the parameters */ |
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431 assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source)); |
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432 assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div)); |
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433 |
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434 tmpreg = RCC->CFGR2; |
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435 /* Clear PREDIV1[3:0] and PREDIV1SRC bits */ |
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436 tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); |
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437 /* Set the PREDIV1 clock source and division factor */ |
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438 tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ; |
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439 /* Store the new value */ |
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440 RCC->CFGR2 = tmpreg; |
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441 } |
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442 #endif |
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443 |
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444 #ifdef STM32F10X_CL |
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445 /** |
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446 * @brief Configures the PREDIV2 division factor. |
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447 * @note |
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448 * - This function must be used only when both PLL2 and PLL3 are disabled. |
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449 * - This function applies only to STM32 Connectivity line devices. |
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450 * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor. |
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451 * This parameter can be RCC_PREDIV2_Divx where x:[1,16] |
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452 * @retval None |
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453 */ |
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454 void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) |
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455 { |
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456 uint32_t tmpreg = 0; |
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457 |
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458 /* Check the parameters */ |
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459 assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div)); |
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460 |
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461 tmpreg = RCC->CFGR2; |
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462 /* Clear PREDIV2[3:0] bits */ |
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463 tmpreg &= ~CFGR2_PREDIV2; |
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464 /* Set the PREDIV2 division factor */ |
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465 tmpreg |= RCC_PREDIV2_Div; |
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466 /* Store the new value */ |
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467 RCC->CFGR2 = tmpreg; |
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468 } |
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469 |
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470 /** |
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471 * @brief Configures the PLL2 multiplication factor. |
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472 * @note |
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473 * - This function must be used only when the PLL2 is disabled. |
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474 * - This function applies only to STM32 Connectivity line devices. |
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475 * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor. |
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476 * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} |
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477 * @retval None |
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478 */ |
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479 void RCC_PLL2Config(uint32_t RCC_PLL2Mul) |
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|
480 { |
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481 uint32_t tmpreg = 0; |
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482 |
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parents:
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483 /* Check the parameters */ |
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484 assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul)); |
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485 |
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486 tmpreg = RCC->CFGR2; |
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487 /* Clear PLL2Mul[3:0] bits */ |
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488 tmpreg &= ~CFGR2_PLL2MUL; |
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parents:
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changeset
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489 /* Set the PLL2 configuration bits */ |
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490 tmpreg |= RCC_PLL2Mul; |
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parents:
diff
changeset
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491 /* Store the new value */ |
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492 RCC->CFGR2 = tmpreg; |
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493 } |
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parents:
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494 |
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495 |
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496 /** |
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497 * @brief Enables or disables the PLL2. |
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498 * @note |
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499 * - The PLL2 can not be disabled if it is used indirectly as system clock |
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500 * (i.e. it is used as PLL clock entry that is used as System clock). |
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501 * - This function applies only to STM32 Connectivity line devices. |
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502 * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE. |
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503 * @retval None |
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504 */ |
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505 void RCC_PLL2Cmd(FunctionalState NewState) |
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506 { |
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507 /* Check the parameters */ |
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508 assert_param(IS_FUNCTIONAL_STATE(NewState)); |
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parents:
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|
509 |
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510 *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState; |
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511 } |
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parents:
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512 |
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parents:
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513 |
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parents:
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514 /** |
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515 * @brief Configures the PLL3 multiplication factor. |
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516 * @note |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
517 * - This function must be used only when the PLL3 is disabled. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
518 * - This function applies only to STM32 Connectivity line devices. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
519 * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
520 * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20} |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
521 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
522 */ |
c59513fd84fb
Initial commit of STM32 test code.
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parents:
diff
changeset
|
523 void RCC_PLL3Config(uint32_t RCC_PLL3Mul) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
524 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
525 uint32_t tmpreg = 0; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
526 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
527 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
528 assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
529 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
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530 tmpreg = RCC->CFGR2; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
531 /* Clear PLL3Mul[3:0] bits */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
532 tmpreg &= ~CFGR2_PLL3MUL; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
533 /* Set the PLL3 configuration bits */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
534 tmpreg |= RCC_PLL3Mul; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
535 /* Store the new value */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
536 RCC->CFGR2 = tmpreg; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
537 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
538 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
539 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
540 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
541 * @brief Enables or disables the PLL3. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
542 * @note This function applies only to STM32 Connectivity line devices. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
543 * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
544 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
545 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
546 void RCC_PLL3Cmd(FunctionalState NewState) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
547 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
548 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
549 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
550 assert_param(IS_FUNCTIONAL_STATE(NewState)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
551 *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
552 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
553 #endif /* STM32F10X_CL */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
554 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
555 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
556 * @brief Configures the system clock (SYSCLK). |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
557 * @param RCC_SYSCLKSource: specifies the clock source used as system clock. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
558 * This parameter can be one of the following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
559 * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
560 * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
561 * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
562 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
563 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
564 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
565 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
566 uint32_t tmpreg = 0; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
567 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
568 assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
569 tmpreg = RCC->CFGR; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
570 /* Clear SW[1:0] bits */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
571 tmpreg &= CFGR_SW_Mask; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
572 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
573 tmpreg |= RCC_SYSCLKSource; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
574 /* Store the new value */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
575 RCC->CFGR = tmpreg; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
576 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
577 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
578 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
579 * @brief Returns the clock source used as system clock. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
580 * @param None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
581 * @retval The clock source used as system clock. The returned value can |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
582 * be one of the following: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
583 * - 0x00: HSI used as system clock |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
584 * - 0x04: HSE used as system clock |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
585 * - 0x08: PLL used as system clock |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
586 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
587 uint8_t RCC_GetSYSCLKSource(void) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
588 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
589 return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
590 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
591 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
592 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
593 * @brief Configures the AHB clock (HCLK). |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
594 * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
595 * the system clock (SYSCLK). |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
596 * This parameter can be one of the following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
597 * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
598 * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
599 * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
600 * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
601 * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
602 * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
603 * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
604 * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
605 * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
606 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
607 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
608 void RCC_HCLKConfig(uint32_t RCC_SYSCLK) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
609 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
610 uint32_t tmpreg = 0; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
611 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
612 assert_param(IS_RCC_HCLK(RCC_SYSCLK)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
613 tmpreg = RCC->CFGR; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
614 /* Clear HPRE[3:0] bits */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
615 tmpreg &= CFGR_HPRE_Reset_Mask; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
616 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
617 tmpreg |= RCC_SYSCLK; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
618 /* Store the new value */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
619 RCC->CFGR = tmpreg; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
620 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
621 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
622 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
623 * @brief Configures the Low Speed APB clock (PCLK1). |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
624 * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
625 * the AHB clock (HCLK). |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
626 * This parameter can be one of the following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
627 * @arg RCC_HCLK_Div1: APB1 clock = HCLK |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
628 * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
629 * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
630 * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
631 * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
632 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
633 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
634 void RCC_PCLK1Config(uint32_t RCC_HCLK) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
635 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
636 uint32_t tmpreg = 0; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
637 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
638 assert_param(IS_RCC_PCLK(RCC_HCLK)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
639 tmpreg = RCC->CFGR; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
640 /* Clear PPRE1[2:0] bits */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
641 tmpreg &= CFGR_PPRE1_Reset_Mask; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
642 /* Set PPRE1[2:0] bits according to RCC_HCLK value */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
643 tmpreg |= RCC_HCLK; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
644 /* Store the new value */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
645 RCC->CFGR = tmpreg; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
646 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
647 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
648 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
649 * @brief Configures the High Speed APB clock (PCLK2). |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
650 * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
651 * the AHB clock (HCLK). |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
652 * This parameter can be one of the following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
653 * @arg RCC_HCLK_Div1: APB2 clock = HCLK |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
654 * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
655 * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
656 * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
657 * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
658 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
659 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
660 void RCC_PCLK2Config(uint32_t RCC_HCLK) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
661 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
662 uint32_t tmpreg = 0; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
663 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
664 assert_param(IS_RCC_PCLK(RCC_HCLK)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
665 tmpreg = RCC->CFGR; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
666 /* Clear PPRE2[2:0] bits */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
667 tmpreg &= CFGR_PPRE2_Reset_Mask; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
668 /* Set PPRE2[2:0] bits according to RCC_HCLK value */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
669 tmpreg |= RCC_HCLK << 3; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
670 /* Store the new value */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
671 RCC->CFGR = tmpreg; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
672 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
673 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
674 /** |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
675 * @brief Enables or disables the specified RCC interrupts. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
676 * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
677 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
678 * For @b STM32_Connectivity_line_devices, this parameter can be any combination |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
679 * of the following values |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
680 * @arg RCC_IT_LSIRDY: LSI ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
681 * @arg RCC_IT_LSERDY: LSE ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
682 * @arg RCC_IT_HSIRDY: HSI ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
683 * @arg RCC_IT_HSERDY: HSE ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
684 * @arg RCC_IT_PLLRDY: PLL ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
685 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
686 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
687 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
688 * For @b other_STM32_devices, this parameter can be any combination of the |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
689 * following values |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
690 * @arg RCC_IT_LSIRDY: LSI ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
691 * @arg RCC_IT_LSERDY: LSE ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
692 * @arg RCC_IT_HSIRDY: HSI ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
693 * @arg RCC_IT_HSERDY: HSE ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
694 * @arg RCC_IT_PLLRDY: PLL ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
695 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
696 * @param NewState: new state of the specified RCC interrupts. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
697 * This parameter can be: ENABLE or DISABLE. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
698 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
699 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
700 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
701 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
702 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
703 assert_param(IS_RCC_IT(RCC_IT)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
704 assert_param(IS_FUNCTIONAL_STATE(NewState)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
705 if (NewState != DISABLE) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
706 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
707 /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
708 *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
709 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
710 else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
711 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
712 /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
713 *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
714 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
715 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
716 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
717 #ifndef STM32F10X_CL |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
718 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
719 * @brief Configures the USB clock (USBCLK). |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
720 * @param RCC_USBCLKSource: specifies the USB clock source. This clock is |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
721 * derived from the PLL output. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
722 * This parameter can be one of the following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
723 * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
724 * clock source |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
725 * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
726 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
727 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
728 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
729 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
730 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
731 assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
732 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
733 *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
734 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
735 #else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
736 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
737 * @brief Configures the USB OTG FS clock (OTGFSCLK). |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
738 * This function applies only to STM32 Connectivity line devices. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
739 * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
740 * This clock is derived from the PLL output. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
741 * This parameter can be one of the following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
742 * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
743 * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
744 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
745 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
746 void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
747 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
748 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
749 assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
750 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
751 *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
752 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
753 #endif /* STM32F10X_CL */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
754 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
755 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
756 * @brief Configures the ADC clock (ADCCLK). |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
757 * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
758 * the APB2 clock (PCLK2). |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
759 * This parameter can be one of the following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
760 * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
761 * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
762 * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
763 * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
764 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
765 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
766 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
767 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
768 uint32_t tmpreg = 0; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
769 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
770 assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
771 tmpreg = RCC->CFGR; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
772 /* Clear ADCPRE[1:0] bits */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
773 tmpreg &= CFGR_ADCPRE_Reset_Mask; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
774 /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
775 tmpreg |= RCC_PCLK2; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
776 /* Store the new value */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
777 RCC->CFGR = tmpreg; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
778 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
779 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
780 #ifdef STM32F10X_CL |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
781 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
782 * @brief Configures the I2S2 clock source(I2S2CLK). |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
783 * @note |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
784 * - This function must be called before enabling I2S2 APB clock. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
785 * - This function applies only to STM32 Connectivity line devices. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
786 * @param RCC_I2S2CLKSource: specifies the I2S2 clock source. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
787 * This parameter can be one of the following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
788 * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
789 * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
790 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
791 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
792 void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
793 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
794 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
795 assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
796 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
797 *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
798 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
799 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
800 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
801 * @brief Configures the I2S3 clock source(I2S2CLK). |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
802 * @note |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
803 * - This function must be called before enabling I2S3 APB clock. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
804 * - This function applies only to STM32 Connectivity line devices. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
805 * @param RCC_I2S3CLKSource: specifies the I2S3 clock source. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
806 * This parameter can be one of the following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
807 * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
808 * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
809 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
810 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
811 void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
812 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
813 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
814 assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
815 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
816 *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
817 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
818 #endif /* STM32F10X_CL */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
819 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
820 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
821 * @brief Configures the External Low Speed oscillator (LSE). |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
822 * @param RCC_LSE: specifies the new state of the LSE. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
823 * This parameter can be one of the following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
824 * @arg RCC_LSE_OFF: LSE oscillator OFF |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
825 * @arg RCC_LSE_ON: LSE oscillator ON |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
826 * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
827 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
828 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
829 void RCC_LSEConfig(uint8_t RCC_LSE) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
830 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
831 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
832 assert_param(IS_RCC_LSE(RCC_LSE)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
833 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
834 /* Reset LSEON bit */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
835 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
836 /* Reset LSEBYP bit */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
837 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
838 /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
839 switch(RCC_LSE) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
840 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
841 case RCC_LSE_ON: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
842 /* Set LSEON bit */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
843 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
844 break; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
845 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
846 case RCC_LSE_Bypass: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
847 /* Set LSEBYP and LSEON bits */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
848 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
849 break; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
850 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
851 default: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
852 break; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
853 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
854 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
855 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
856 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
857 * @brief Enables or disables the Internal Low Speed oscillator (LSI). |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
858 * @note LSI can not be disabled if the IWDG is running. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
859 * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
860 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
861 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
862 void RCC_LSICmd(FunctionalState NewState) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
863 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
864 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
865 assert_param(IS_FUNCTIONAL_STATE(NewState)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
866 *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
867 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
868 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
869 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
870 * @brief Configures the RTC clock (RTCCLK). |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
871 * @note Once the RTC clock is selected it can't be changed unless the Backup domain is reset. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
872 * @param RCC_RTCCLKSource: specifies the RTC clock source. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
873 * This parameter can be one of the following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
874 * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
875 * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
876 * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
877 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
878 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
879 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
880 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
881 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
882 assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
883 /* Select the RTC clock source */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
884 RCC->BDCR |= RCC_RTCCLKSource; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
885 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
886 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
887 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
888 * @brief Enables or disables the RTC clock. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
889 * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
890 * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
891 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
892 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
893 void RCC_RTCCLKCmd(FunctionalState NewState) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
894 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
895 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
896 assert_param(IS_FUNCTIONAL_STATE(NewState)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
897 *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
898 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
899 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
900 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
901 * @brief Returns the frequencies of different on chip clocks. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
902 * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
903 * the clocks frequencies. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
904 * @note The result of this function could be not correct when using |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
905 * fractional value for HSE crystal. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
906 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
907 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
908 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
909 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
910 uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
911 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
912 #ifdef STM32F10X_CL |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
913 uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
914 #endif /* STM32F10X_CL */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
915 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
916 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
917 uint32_t prediv1factor = 0; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
918 #endif |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
919 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
920 /* Get SYSCLK source -------------------------------------------------------*/ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
921 tmp = RCC->CFGR & CFGR_SWS_Mask; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
922 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
923 switch (tmp) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
924 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
925 case 0x00: /* HSI used as system clock */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
926 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
927 break; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
928 case 0x04: /* HSE used as system clock */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
929 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
930 break; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
931 case 0x08: /* PLL used as system clock */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
932 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
933 /* Get PLL clock source and multiplication factor ----------------------*/ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
934 pllmull = RCC->CFGR & CFGR_PLLMull_Mask; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
935 pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
936 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
937 #ifndef STM32F10X_CL |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
938 pllmull = ( pllmull >> 18) + 2; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
939 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
940 if (pllsource == 0x00) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
941 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
942 RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
943 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
944 else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
945 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
946 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
947 prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
948 /* HSE oscillator clock selected as PREDIV1 clock entry */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
949 RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
950 #else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
951 /* HSE selected as PLL clock entry */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
952 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
953 {/* HSE oscillator clock divided by 2 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
954 RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
955 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
956 else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
957 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
958 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
959 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
960 #endif |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
961 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
962 #else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
963 pllmull = pllmull >> 18; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
964 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
965 if (pllmull != 0x0D) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
966 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
967 pllmull += 2; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
968 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
969 else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
970 { /* PLL multiplication factor = PLL input clock * 6.5 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
971 pllmull = 13 / 2; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
972 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
973 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
974 if (pllsource == 0x00) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
975 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
976 RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
977 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
978 else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
979 {/* PREDIV1 selected as PLL clock entry */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
980 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
981 /* Get PREDIV1 clock source and division factor */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
982 prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
983 prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
984 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
985 if (prediv1source == 0) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
986 { /* HSE oscillator clock selected as PREDIV1 clock entry */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
987 RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
988 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
989 else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
990 {/* PLL2 clock selected as PREDIV1 clock entry */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
991 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
992 /* Get PREDIV2 division factor and PLL2 multiplication factor */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
993 prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
994 pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
995 RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
996 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
997 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
998 #endif /* STM32F10X_CL */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
999 break; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1000 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1001 default: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1002 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1003 break; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1004 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1005 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1006 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1007 /* Get HCLK prescaler */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1008 tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1009 tmp = tmp >> 4; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1010 presc = APBAHBPrescTable[tmp]; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1011 /* HCLK clock frequency */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1012 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1013 /* Get PCLK1 prescaler */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1014 tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1015 tmp = tmp >> 8; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1016 presc = APBAHBPrescTable[tmp]; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1017 /* PCLK1 clock frequency */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1018 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1019 /* Get PCLK2 prescaler */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1020 tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1021 tmp = tmp >> 11; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1022 presc = APBAHBPrescTable[tmp]; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1023 /* PCLK2 clock frequency */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1024 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1025 /* Get ADCCLK prescaler */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1026 tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1027 tmp = tmp >> 14; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1028 presc = ADCPrescTable[tmp]; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1029 /* ADCCLK clock frequency */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1030 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1031 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1032 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1033 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1034 * @brief Enables or disables the AHB peripheral clock. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1035 * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1036 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1037 * For @b STM32_Connectivity_line_devices, this parameter can be any combination |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1038 * of the following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1039 * @arg RCC_AHBPeriph_DMA1 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1040 * @arg RCC_AHBPeriph_DMA2 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1041 * @arg RCC_AHBPeriph_SRAM |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1042 * @arg RCC_AHBPeriph_FLITF |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1043 * @arg RCC_AHBPeriph_CRC |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1044 * @arg RCC_AHBPeriph_OTG_FS |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1045 * @arg RCC_AHBPeriph_ETH_MAC |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1046 * @arg RCC_AHBPeriph_ETH_MAC_Tx |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1047 * @arg RCC_AHBPeriph_ETH_MAC_Rx |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1048 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1049 * For @b other_STM32_devices, this parameter can be any combination of the |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1050 * following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1051 * @arg RCC_AHBPeriph_DMA1 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1052 * @arg RCC_AHBPeriph_DMA2 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1053 * @arg RCC_AHBPeriph_SRAM |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1054 * @arg RCC_AHBPeriph_FLITF |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1055 * @arg RCC_AHBPeriph_CRC |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1056 * @arg RCC_AHBPeriph_FSMC |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1057 * @arg RCC_AHBPeriph_SDIO |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1058 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1059 * @note SRAM and FLITF clock can be disabled only during sleep mode. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1060 * @param NewState: new state of the specified peripheral clock. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1061 * This parameter can be: ENABLE or DISABLE. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1062 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1063 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1064 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1065 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1066 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1067 assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1068 assert_param(IS_FUNCTIONAL_STATE(NewState)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1069 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1070 if (NewState != DISABLE) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1071 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1072 RCC->AHBENR |= RCC_AHBPeriph; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1073 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1074 else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1075 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1076 RCC->AHBENR &= ~RCC_AHBPeriph; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1077 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1078 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1079 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1080 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1081 * @brief Enables or disables the High Speed APB (APB2) peripheral clock. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1082 * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1083 * This parameter can be any combination of the following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1084 * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1085 * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1086 * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1087 * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1088 * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1089 * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1090 * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1091 * @param NewState: new state of the specified peripheral clock. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1092 * This parameter can be: ENABLE or DISABLE. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1093 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1094 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1095 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1096 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1097 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1098 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1099 assert_param(IS_FUNCTIONAL_STATE(NewState)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1100 if (NewState != DISABLE) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1101 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1102 RCC->APB2ENR |= RCC_APB2Periph; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1103 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1104 else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1105 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1106 RCC->APB2ENR &= ~RCC_APB2Periph; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1107 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1108 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1109 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1110 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1111 * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1112 * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1113 * This parameter can be any combination of the following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1114 * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1115 * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1116 * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1117 * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1118 * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1119 * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1120 * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1121 * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1122 * @param NewState: new state of the specified peripheral clock. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1123 * This parameter can be: ENABLE or DISABLE. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1124 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1125 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1126 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1127 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1128 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1129 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1130 assert_param(IS_FUNCTIONAL_STATE(NewState)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1131 if (NewState != DISABLE) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1132 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1133 RCC->APB1ENR |= RCC_APB1Periph; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1134 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1135 else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1136 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1137 RCC->APB1ENR &= ~RCC_APB1Periph; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1138 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1139 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1140 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1141 #ifdef STM32F10X_CL |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1142 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1143 * @brief Forces or releases AHB peripheral reset. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1144 * @note This function applies only to STM32 Connectivity line devices. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1145 * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1146 * This parameter can be any combination of the following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1147 * @arg RCC_AHBPeriph_OTG_FS |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1148 * @arg RCC_AHBPeriph_ETH_MAC |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1149 * @param NewState: new state of the specified peripheral reset. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1150 * This parameter can be: ENABLE or DISABLE. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1151 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1152 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1153 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1154 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1155 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1156 assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1157 assert_param(IS_FUNCTIONAL_STATE(NewState)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1158 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1159 if (NewState != DISABLE) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1160 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1161 RCC->AHBRSTR |= RCC_AHBPeriph; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1162 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1163 else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1164 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1165 RCC->AHBRSTR &= ~RCC_AHBPeriph; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1166 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1167 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1168 #endif /* STM32F10X_CL */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1169 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1170 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1171 * @brief Forces or releases High Speed APB (APB2) peripheral reset. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1172 * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1173 * This parameter can be any combination of the following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1174 * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1175 * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1176 * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1177 * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1178 * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1179 * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1180 * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1181 * @param NewState: new state of the specified peripheral reset. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1182 * This parameter can be: ENABLE or DISABLE. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1183 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1184 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1185 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1186 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1187 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1188 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1189 assert_param(IS_FUNCTIONAL_STATE(NewState)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1190 if (NewState != DISABLE) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1191 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1192 RCC->APB2RSTR |= RCC_APB2Periph; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1193 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1194 else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1195 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1196 RCC->APB2RSTR &= ~RCC_APB2Periph; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1197 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1198 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1199 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1200 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1201 * @brief Forces or releases Low Speed APB (APB1) peripheral reset. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1202 * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1203 * This parameter can be any combination of the following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1204 * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1205 * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1206 * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1207 * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1208 * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1209 * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1210 * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1211 * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1212 * @param NewState: new state of the specified peripheral clock. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1213 * This parameter can be: ENABLE or DISABLE. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1214 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1215 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1216 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1217 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1218 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1219 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1220 assert_param(IS_FUNCTIONAL_STATE(NewState)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1221 if (NewState != DISABLE) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1222 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1223 RCC->APB1RSTR |= RCC_APB1Periph; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1224 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1225 else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1226 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1227 RCC->APB1RSTR &= ~RCC_APB1Periph; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1228 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1229 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1230 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1231 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1232 * @brief Forces or releases the Backup domain reset. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1233 * @param NewState: new state of the Backup domain reset. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1234 * This parameter can be: ENABLE or DISABLE. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1235 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1236 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1237 void RCC_BackupResetCmd(FunctionalState NewState) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1238 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1239 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1240 assert_param(IS_FUNCTIONAL_STATE(NewState)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1241 *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1242 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1243 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1244 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1245 * @brief Enables or disables the Clock Security System. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1246 * @param NewState: new state of the Clock Security System.. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1247 * This parameter can be: ENABLE or DISABLE. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1248 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1249 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1250 void RCC_ClockSecuritySystemCmd(FunctionalState NewState) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1251 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1252 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1253 assert_param(IS_FUNCTIONAL_STATE(NewState)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1254 *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1255 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1256 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1257 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1258 * @brief Selects the clock source to output on MCO pin. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1259 * @param RCC_MCO: specifies the clock source to output. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1260 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1261 * For @b STM32_Connectivity_line_devices, this parameter can be one of the |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1262 * following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1263 * @arg RCC_MCO_NoClock: No clock selected |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1264 * @arg RCC_MCO_SYSCLK: System clock selected |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1265 * @arg RCC_MCO_HSI: HSI oscillator clock selected |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1266 * @arg RCC_MCO_HSE: HSE oscillator clock selected |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1267 * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1268 * @arg RCC_MCO_PLL2CLK: PLL2 clock selected |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1269 * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1270 * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1271 * @arg RCC_MCO_PLL3CLK: PLL3 clock selected |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1272 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1273 * For @b other_STM32_devices, this parameter can be one of the following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1274 * @arg RCC_MCO_NoClock: No clock selected |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1275 * @arg RCC_MCO_SYSCLK: System clock selected |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1276 * @arg RCC_MCO_HSI: HSI oscillator clock selected |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1277 * @arg RCC_MCO_HSE: HSE oscillator clock selected |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1278 * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1279 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1280 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1281 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1282 void RCC_MCOConfig(uint8_t RCC_MCO) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1283 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1284 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1285 assert_param(IS_RCC_MCO(RCC_MCO)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1286 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1287 /* Perform Byte access to MCO bits to select the MCO source */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1288 *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1289 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1290 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1291 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1292 * @brief Checks whether the specified RCC flag is set or not. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1293 * @param RCC_FLAG: specifies the flag to check. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1294 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1295 * For @b STM32_Connectivity_line_devices, this parameter can be one of the |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1296 * following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1297 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1298 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1299 * @arg RCC_FLAG_PLLRDY: PLL clock ready |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1300 * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1301 * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1302 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1303 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1304 * @arg RCC_FLAG_PINRST: Pin reset |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1305 * @arg RCC_FLAG_PORRST: POR/PDR reset |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1306 * @arg RCC_FLAG_SFTRST: Software reset |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1307 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1308 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1309 * @arg RCC_FLAG_LPWRRST: Low Power reset |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1310 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1311 * For @b other_STM32_devices, this parameter can be one of the following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1312 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1313 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1314 * @arg RCC_FLAG_PLLRDY: PLL clock ready |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1315 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1316 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1317 * @arg RCC_FLAG_PINRST: Pin reset |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1318 * @arg RCC_FLAG_PORRST: POR/PDR reset |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1319 * @arg RCC_FLAG_SFTRST: Software reset |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1320 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1321 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1322 * @arg RCC_FLAG_LPWRRST: Low Power reset |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1323 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1324 * @retval The new state of RCC_FLAG (SET or RESET). |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1325 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1326 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1327 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1328 uint32_t tmp = 0; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1329 uint32_t statusreg = 0; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1330 FlagStatus bitstatus = RESET; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1331 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1332 assert_param(IS_RCC_FLAG(RCC_FLAG)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1333 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1334 /* Get the RCC register index */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1335 tmp = RCC_FLAG >> 5; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1336 if (tmp == 1) /* The flag to check is in CR register */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1337 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1338 statusreg = RCC->CR; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1339 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1340 else if (tmp == 2) /* The flag to check is in BDCR register */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1341 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1342 statusreg = RCC->BDCR; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1343 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1344 else /* The flag to check is in CSR register */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1345 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1346 statusreg = RCC->CSR; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1347 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1348 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1349 /* Get the flag position */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1350 tmp = RCC_FLAG & FLAG_Mask; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1351 if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1352 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1353 bitstatus = SET; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1354 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1355 else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1356 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1357 bitstatus = RESET; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1358 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1359 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1360 /* Return the flag status */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1361 return bitstatus; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1362 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1363 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1364 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1365 * @brief Clears the RCC reset flags. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1366 * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1367 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1368 * @param None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1369 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1370 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1371 void RCC_ClearFlag(void) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1372 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1373 /* Set RMVF bit to clear the reset flags */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1374 RCC->CSR |= CSR_RMVF_Set; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1375 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1376 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1377 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1378 * @brief Checks whether the specified RCC interrupt has occurred or not. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1379 * @param RCC_IT: specifies the RCC interrupt source to check. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1380 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1381 * For @b STM32_Connectivity_line_devices, this parameter can be one of the |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1382 * following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1383 * @arg RCC_IT_LSIRDY: LSI ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1384 * @arg RCC_IT_LSERDY: LSE ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1385 * @arg RCC_IT_HSIRDY: HSI ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1386 * @arg RCC_IT_HSERDY: HSE ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1387 * @arg RCC_IT_PLLRDY: PLL ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1388 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1389 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1390 * @arg RCC_IT_CSS: Clock Security System interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1391 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1392 * For @b other_STM32_devices, this parameter can be one of the following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1393 * @arg RCC_IT_LSIRDY: LSI ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1394 * @arg RCC_IT_LSERDY: LSE ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1395 * @arg RCC_IT_HSIRDY: HSI ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1396 * @arg RCC_IT_HSERDY: HSE ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1397 * @arg RCC_IT_PLLRDY: PLL ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1398 * @arg RCC_IT_CSS: Clock Security System interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1399 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1400 * @retval The new state of RCC_IT (SET or RESET). |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1401 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1402 ITStatus RCC_GetITStatus(uint8_t RCC_IT) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1403 { |
c59513fd84fb
Initial commit of STM32 test code.
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parents:
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1404 ITStatus bitstatus = RESET; |
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Initial commit of STM32 test code.
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1405 /* Check the parameters */ |
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Initial commit of STM32 test code.
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parents:
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1406 assert_param(IS_RCC_GET_IT(RCC_IT)); |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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1407 |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
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1408 /* Check the status of the specified RCC interrupt */ |
c59513fd84fb
Initial commit of STM32 test code.
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parents:
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1409 if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1410 { |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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1411 bitstatus = SET; |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1412 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1413 else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1414 { |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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1415 bitstatus = RESET; |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1416 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1417 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1418 /* Return the RCC_IT status */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1419 return bitstatus; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1420 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1421 |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1422 /** |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1423 * @brief Clears the RCC's interrupt pending bits. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1424 * @param RCC_IT: specifies the interrupt pending bit to clear. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1425 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1426 * For @b STM32_Connectivity_line_devices, this parameter can be any combination |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1427 * of the following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1428 * @arg RCC_IT_LSIRDY: LSI ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1429 * @arg RCC_IT_LSERDY: LSE ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1430 * @arg RCC_IT_HSIRDY: HSI ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1431 * @arg RCC_IT_HSERDY: HSE ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1432 * @arg RCC_IT_PLLRDY: PLL ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1433 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1434 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1435 * @arg RCC_IT_CSS: Clock Security System interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1436 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1437 * For @b other_STM32_devices, this parameter can be any combination of the |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1438 * following values: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1439 * @arg RCC_IT_LSIRDY: LSI ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1440 * @arg RCC_IT_LSERDY: LSE ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1441 * @arg RCC_IT_HSIRDY: HSI ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1442 * @arg RCC_IT_HSERDY: HSE ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1443 * @arg RCC_IT_PLLRDY: PLL ready interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1444 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1445 * @arg RCC_IT_CSS: Clock Security System interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1446 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1447 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1448 void RCC_ClearITPendingBit(uint8_t RCC_IT) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1449 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1450 /* Check the parameters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1451 assert_param(IS_RCC_CLEAR_IT(RCC_IT)); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1452 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1453 /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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1454 pending bits */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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1455 *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1456 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1457 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1458 /** |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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1459 * @} |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1460 */ |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1461 |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1462 /** |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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1463 * @} |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1464 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1465 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1466 /** |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1467 * @} |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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|
1468 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
1469 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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1470 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |