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annotate libs/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h @ 0:c59513fd84fb

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Initial commit of STM32 test code.
author Daniel O'Connor <darius@dons.net.au>
date Mon, 03 Oct 2011 21:19:15 +1030
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1 /**
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2 ******************************************************************************
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3 * @file stm32f10x_dma.h
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4 * @author MCD Application Team
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5 * @version V3.5.0
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6 * @date 11-March-2011
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7 * @brief This file contains all the functions prototypes for the DMA firmware
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8 * library.
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9 ******************************************************************************
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10 * @attention
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11 *
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12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 *
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19 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
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20 ******************************************************************************
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21 */
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22
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23 /* Define to prevent recursive inclusion -------------------------------------*/
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24 #ifndef __STM32F10x_DMA_H
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25 #define __STM32F10x_DMA_H
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26
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27 #ifdef __cplusplus
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28 extern "C" {
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29 #endif
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30
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31 /* Includes ------------------------------------------------------------------*/
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32 #include "stm32f10x.h"
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33
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34 /** @addtogroup STM32F10x_StdPeriph_Driver
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35 * @{
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36 */
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37
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38 /** @addtogroup DMA
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39 * @{
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40 */
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41
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42 /** @defgroup DMA_Exported_Types
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43 * @{
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44 */
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45
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46 /**
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47 * @brief DMA Init structure definition
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48 */
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49
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50 typedef struct
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51 {
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52 uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
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53
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54 uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
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55
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56 uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
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57 This parameter can be a value of @ref DMA_data_transfer_direction */
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58
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59 uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
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60 The data unit is equal to the configuration set in DMA_PeripheralDataSize
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61 or DMA_MemoryDataSize members depending in the transfer direction. */
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62
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63 uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
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64 This parameter can be a value of @ref DMA_peripheral_incremented_mode */
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65
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66 uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
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67 This parameter can be a value of @ref DMA_memory_incremented_mode */
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68
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69 uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
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70 This parameter can be a value of @ref DMA_peripheral_data_size */
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71
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72 uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
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73 This parameter can be a value of @ref DMA_memory_data_size */
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74
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75 uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
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76 This parameter can be a value of @ref DMA_circular_normal_mode.
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77 @note: The circular buffer mode cannot be used if the memory-to-memory
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78 data transfer is configured on the selected Channel */
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79
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80 uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
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81 This parameter can be a value of @ref DMA_priority_level */
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82
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83 uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
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84 This parameter can be a value of @ref DMA_memory_to_memory */
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85 }DMA_InitTypeDef;
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86
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87 /**
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88 * @}
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89 */
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90
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91 /** @defgroup DMA_Exported_Constants
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92 * @{
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93 */
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94
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95 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
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96 ((PERIPH) == DMA1_Channel2) || \
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97 ((PERIPH) == DMA1_Channel3) || \
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98 ((PERIPH) == DMA1_Channel4) || \
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99 ((PERIPH) == DMA1_Channel5) || \
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100 ((PERIPH) == DMA1_Channel6) || \
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101 ((PERIPH) == DMA1_Channel7) || \
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102 ((PERIPH) == DMA2_Channel1) || \
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103 ((PERIPH) == DMA2_Channel2) || \
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104 ((PERIPH) == DMA2_Channel3) || \
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105 ((PERIPH) == DMA2_Channel4) || \
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106 ((PERIPH) == DMA2_Channel5))
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107
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108 /** @defgroup DMA_data_transfer_direction
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109 * @{
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110 */
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111
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112 #define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
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113 #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
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114 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
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115 ((DIR) == DMA_DIR_PeripheralSRC))
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116 /**
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117 * @}
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118 */
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119
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120 /** @defgroup DMA_peripheral_incremented_mode
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121 * @{
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122 */
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123
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124 #define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
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125 #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
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126 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
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127 ((STATE) == DMA_PeripheralInc_Disable))
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128 /**
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129 * @}
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130 */
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131
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132 /** @defgroup DMA_memory_incremented_mode
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133 * @{
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134 */
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135
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136 #define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
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137 #define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
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138 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
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139 ((STATE) == DMA_MemoryInc_Disable))
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140 /**
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141 * @}
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142 */
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143
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144 /** @defgroup DMA_peripheral_data_size
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145 * @{
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146 */
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147
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148 #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
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149 #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
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150 #define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
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151 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
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152 ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
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153 ((SIZE) == DMA_PeripheralDataSize_Word))
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154 /**
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155 * @}
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156 */
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157
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158 /** @defgroup DMA_memory_data_size
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159 * @{
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160 */
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161
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162 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
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163 #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
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164 #define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
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165 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
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166 ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
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167 ((SIZE) == DMA_MemoryDataSize_Word))
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168 /**
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169 * @}
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170 */
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171
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172 /** @defgroup DMA_circular_normal_mode
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173 * @{
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174 */
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175
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176 #define DMA_Mode_Circular ((uint32_t)0x00000020)
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177 #define DMA_Mode_Normal ((uint32_t)0x00000000)
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178 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
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179 /**
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180 * @}
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181 */
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182
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183 /** @defgroup DMA_priority_level
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184 * @{
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185 */
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186
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187 #define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
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188 #define DMA_Priority_High ((uint32_t)0x00002000)
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189 #define DMA_Priority_Medium ((uint32_t)0x00001000)
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190 #define DMA_Priority_Low ((uint32_t)0x00000000)
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191 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
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192 ((PRIORITY) == DMA_Priority_High) || \
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193 ((PRIORITY) == DMA_Priority_Medium) || \
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194 ((PRIORITY) == DMA_Priority_Low))
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195 /**
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196 * @}
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197 */
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198
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199 /** @defgroup DMA_memory_to_memory
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200 * @{
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201 */
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202
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203 #define DMA_M2M_Enable ((uint32_t)0x00004000)
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204 #define DMA_M2M_Disable ((uint32_t)0x00000000)
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205 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
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206
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207 /**
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208 * @}
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209 */
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210
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211 /** @defgroup DMA_interrupts_definition
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212 * @{
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213 */
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214
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215 #define DMA_IT_TC ((uint32_t)0x00000002)
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216 #define DMA_IT_HT ((uint32_t)0x00000004)
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217 #define DMA_IT_TE ((uint32_t)0x00000008)
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218 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
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219
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220 #define DMA1_IT_GL1 ((uint32_t)0x00000001)
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221 #define DMA1_IT_TC1 ((uint32_t)0x00000002)
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222 #define DMA1_IT_HT1 ((uint32_t)0x00000004)
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223 #define DMA1_IT_TE1 ((uint32_t)0x00000008)
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224 #define DMA1_IT_GL2 ((uint32_t)0x00000010)
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225 #define DMA1_IT_TC2 ((uint32_t)0x00000020)
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226 #define DMA1_IT_HT2 ((uint32_t)0x00000040)
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227 #define DMA1_IT_TE2 ((uint32_t)0x00000080)
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228 #define DMA1_IT_GL3 ((uint32_t)0x00000100)
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229 #define DMA1_IT_TC3 ((uint32_t)0x00000200)
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230 #define DMA1_IT_HT3 ((uint32_t)0x00000400)
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231 #define DMA1_IT_TE3 ((uint32_t)0x00000800)
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232 #define DMA1_IT_GL4 ((uint32_t)0x00001000)
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233 #define DMA1_IT_TC4 ((uint32_t)0x00002000)
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234 #define DMA1_IT_HT4 ((uint32_t)0x00004000)
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235 #define DMA1_IT_TE4 ((uint32_t)0x00008000)
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236 #define DMA1_IT_GL5 ((uint32_t)0x00010000)
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237 #define DMA1_IT_TC5 ((uint32_t)0x00020000)
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238 #define DMA1_IT_HT5 ((uint32_t)0x00040000)
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239 #define DMA1_IT_TE5 ((uint32_t)0x00080000)
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240 #define DMA1_IT_GL6 ((uint32_t)0x00100000)
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241 #define DMA1_IT_TC6 ((uint32_t)0x00200000)
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242 #define DMA1_IT_HT6 ((uint32_t)0x00400000)
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243 #define DMA1_IT_TE6 ((uint32_t)0x00800000)
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244 #define DMA1_IT_GL7 ((uint32_t)0x01000000)
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245 #define DMA1_IT_TC7 ((uint32_t)0x02000000)
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246 #define DMA1_IT_HT7 ((uint32_t)0x04000000)
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247 #define DMA1_IT_TE7 ((uint32_t)0x08000000)
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248
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249 #define DMA2_IT_GL1 ((uint32_t)0x10000001)
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250 #define DMA2_IT_TC1 ((uint32_t)0x10000002)
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251 #define DMA2_IT_HT1 ((uint32_t)0x10000004)
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252 #define DMA2_IT_TE1 ((uint32_t)0x10000008)
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253 #define DMA2_IT_GL2 ((uint32_t)0x10000010)
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254 #define DMA2_IT_TC2 ((uint32_t)0x10000020)
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255 #define DMA2_IT_HT2 ((uint32_t)0x10000040)
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256 #define DMA2_IT_TE2 ((uint32_t)0x10000080)
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257 #define DMA2_IT_GL3 ((uint32_t)0x10000100)
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258 #define DMA2_IT_TC3 ((uint32_t)0x10000200)
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259 #define DMA2_IT_HT3 ((uint32_t)0x10000400)
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260 #define DMA2_IT_TE3 ((uint32_t)0x10000800)
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261 #define DMA2_IT_GL4 ((uint32_t)0x10001000)
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262 #define DMA2_IT_TC4 ((uint32_t)0x10002000)
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263 #define DMA2_IT_HT4 ((uint32_t)0x10004000)
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264 #define DMA2_IT_TE4 ((uint32_t)0x10008000)
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265 #define DMA2_IT_GL5 ((uint32_t)0x10010000)
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266 #define DMA2_IT_TC5 ((uint32_t)0x10020000)
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267 #define DMA2_IT_HT5 ((uint32_t)0x10040000)
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268 #define DMA2_IT_TE5 ((uint32_t)0x10080000)
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269
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270 #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
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271
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272 #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
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273 ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
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diff changeset
274 ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
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diff changeset
275 ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
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diff changeset
276 ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
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diff changeset
277 ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
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diff changeset
278 ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
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diff changeset
279 ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
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280 ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
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diff changeset
281 ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
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diff changeset
282 ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
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diff changeset
283 ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
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diff changeset
284 ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
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diff changeset
285 ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
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diff changeset
286 ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
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diff changeset
287 ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
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diff changeset
288 ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
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diff changeset
289 ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
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diff changeset
290 ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
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diff changeset
291 ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
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diff changeset
292 ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
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diff changeset
293 ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
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diff changeset
294 ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
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diff changeset
295 ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
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296
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diff changeset
297 /**
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diff changeset
298 * @}
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diff changeset
299 */
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300
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diff changeset
301 /** @defgroup DMA_flags_definition
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diff changeset
302 * @{
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diff changeset
303 */
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304 #define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
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diff changeset
305 #define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
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306 #define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
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307 #define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
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308 #define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
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309 #define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
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310 #define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
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311 #define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
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312 #define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
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313 #define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
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314 #define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
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315 #define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
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316 #define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
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317 #define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
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318 #define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
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319 #define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
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320 #define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
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321 #define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
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322 #define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
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323 #define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
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324 #define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
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325 #define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
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326 #define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
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327 #define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
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328 #define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
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diff changeset
329 #define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
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330 #define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
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331 #define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
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diff changeset
332
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diff changeset
333 #define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
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diff changeset
334 #define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
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diff changeset
335 #define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
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diff changeset
336 #define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
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diff changeset
337 #define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
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diff changeset
338 #define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
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diff changeset
339 #define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
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340 #define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
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341 #define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
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342 #define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
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343 #define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
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344 #define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
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345 #define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
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346 #define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
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diff changeset
347 #define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
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diff changeset
348 #define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
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diff changeset
349 #define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
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350 #define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
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diff changeset
351 #define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
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diff changeset
352 #define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
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353
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diff changeset
354 #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
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diff changeset
355
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diff changeset
356 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
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diff changeset
357 ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
358 ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
359 ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
360 ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
361 ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
362 ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
363 ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
364 ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
365 ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
366 ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
367 ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
368 ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
369 ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
370 ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
371 ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
372 ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
373 ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
374 ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
375 ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
376 ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
377 ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
378 ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
379 ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
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diff changeset
380 /**
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diff changeset
381 * @}
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
382 */
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diff changeset
383
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diff changeset
384 /** @defgroup DMA_Buffer_Size
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diff changeset
385 * @{
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diff changeset
386 */
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diff changeset
387
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diff changeset
388 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
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diff changeset
389
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
390 /**
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
391 * @}
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
392 */
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
393
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
394 /**
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
395 * @}
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
396 */
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
397
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
398 /** @defgroup DMA_Exported_Macros
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diff changeset
399 * @{
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diff changeset
400 */
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
401
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
402 /**
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
403 * @}
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
404 */
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
405
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
406 /** @defgroup DMA_Exported_Functions
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diff changeset
407 * @{
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parents:
diff changeset
408 */
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
409
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
410 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
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diff changeset
411 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
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diff changeset
412 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
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diff changeset
413 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
414 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
415 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
c59513fd84fb Initial commit of STM32 test code.
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416 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
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417 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
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418 void DMA_ClearFlag(uint32_t DMAy_FLAG);
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419 ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
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420 void DMA_ClearITPendingBit(uint32_t DMAy_IT);
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421
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422 #ifdef __cplusplus
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423 }
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424 #endif
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425
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426 #endif /*__STM32F10x_DMA_H */
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427 /**
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428 * @}
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429 */
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430
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431 /**
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432 * @}
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433 */
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434
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435 /**
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436 * @}
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437 */
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438
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439 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/