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annotate libs/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h @ 0:c59513fd84fb

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Initial commit of STM32 test code.
author Daniel O'Connor <darius@dons.net.au>
date Mon, 03 Oct 2011 21:19:15 +1030
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1 /**
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2 ******************************************************************************
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3 * @file stm32f10x_adc.h
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4 * @author MCD Application Team
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5 * @version V3.5.0
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6 * @date 11-March-2011
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7 * @brief This file contains all the functions prototypes for the ADC firmware
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8 * library.
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9 ******************************************************************************
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10 * @attention
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11 *
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12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 *
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19 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
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20 ******************************************************************************
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21 */
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22
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23 /* Define to prevent recursive inclusion -------------------------------------*/
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24 #ifndef __STM32F10x_ADC_H
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25 #define __STM32F10x_ADC_H
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26
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27 #ifdef __cplusplus
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28 extern "C" {
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29 #endif
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30
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31 /* Includes ------------------------------------------------------------------*/
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32 #include "stm32f10x.h"
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33
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34 /** @addtogroup STM32F10x_StdPeriph_Driver
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35 * @{
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36 */
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37
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38 /** @addtogroup ADC
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39 * @{
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40 */
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41
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42 /** @defgroup ADC_Exported_Types
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43 * @{
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44 */
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45
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46 /**
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47 * @brief ADC Init structure definition
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48 */
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49
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50 typedef struct
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51 {
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52 uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or
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53 dual mode.
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54 This parameter can be a value of @ref ADC_mode */
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55
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56 FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in
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57 Scan (multichannels) or Single (one channel) mode.
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58 This parameter can be set to ENABLE or DISABLE */
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59
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60 FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
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61 Continuous or Single mode.
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62 This parameter can be set to ENABLE or DISABLE. */
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63
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64 uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
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65 to digital conversion of regular channels. This parameter
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66 can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
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67
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68 uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
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69 This parameter can be a value of @ref ADC_data_align */
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70
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71 uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted
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72 using the sequencer for regular channel group.
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73 This parameter must range from 1 to 16. */
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74 }ADC_InitTypeDef;
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75 /**
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76 * @}
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77 */
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78
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79 /** @defgroup ADC_Exported_Constants
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80 * @{
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81 */
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82
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83 #define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
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84 ((PERIPH) == ADC2) || \
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85 ((PERIPH) == ADC3))
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86
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87 #define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
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88 ((PERIPH) == ADC3))
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89
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90 /** @defgroup ADC_mode
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91 * @{
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92 */
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93
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94 #define ADC_Mode_Independent ((uint32_t)0x00000000)
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95 #define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
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96 #define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
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97 #define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
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98 #define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
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99 #define ADC_Mode_InjecSimult ((uint32_t)0x00050000)
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100 #define ADC_Mode_RegSimult ((uint32_t)0x00060000)
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101 #define ADC_Mode_FastInterl ((uint32_t)0x00070000)
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102 #define ADC_Mode_SlowInterl ((uint32_t)0x00080000)
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103 #define ADC_Mode_AlterTrig ((uint32_t)0x00090000)
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104
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105 #define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
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106 ((MODE) == ADC_Mode_RegInjecSimult) || \
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107 ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
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108 ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
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109 ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
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110 ((MODE) == ADC_Mode_InjecSimult) || \
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111 ((MODE) == ADC_Mode_RegSimult) || \
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112 ((MODE) == ADC_Mode_FastInterl) || \
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113 ((MODE) == ADC_Mode_SlowInterl) || \
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114 ((MODE) == ADC_Mode_AlterTrig))
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115 /**
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116 * @}
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117 */
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118
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119 /** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
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120 * @{
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121 */
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122
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123 #define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
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124 #define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
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125 #define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
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126 #define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
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127 #define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
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128 #define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
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129
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130 #define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */
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131 #define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
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132
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133 #define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */
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134 #define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */
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135 #define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */
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136 #define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */
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137 #define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */
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138 #define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */
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139
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140 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
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141 ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
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142 ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
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143 ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
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144 ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
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145 ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
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146 ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
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147 ((REGTRIG) == ADC_ExternalTrigConv_None) || \
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148 ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
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149 ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
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150 ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
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151 ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
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152 ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
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153 ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
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154 /**
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155 * @}
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156 */
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157
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158 /** @defgroup ADC_data_align
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159 * @{
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160 */
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161
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162 #define ADC_DataAlign_Right ((uint32_t)0x00000000)
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163 #define ADC_DataAlign_Left ((uint32_t)0x00000800)
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164 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
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165 ((ALIGN) == ADC_DataAlign_Left))
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166 /**
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167 * @}
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168 */
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169
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170 /** @defgroup ADC_channels
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171 * @{
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172 */
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173
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174 #define ADC_Channel_0 ((uint8_t)0x00)
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175 #define ADC_Channel_1 ((uint8_t)0x01)
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176 #define ADC_Channel_2 ((uint8_t)0x02)
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177 #define ADC_Channel_3 ((uint8_t)0x03)
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178 #define ADC_Channel_4 ((uint8_t)0x04)
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179 #define ADC_Channel_5 ((uint8_t)0x05)
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180 #define ADC_Channel_6 ((uint8_t)0x06)
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181 #define ADC_Channel_7 ((uint8_t)0x07)
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182 #define ADC_Channel_8 ((uint8_t)0x08)
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183 #define ADC_Channel_9 ((uint8_t)0x09)
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184 #define ADC_Channel_10 ((uint8_t)0x0A)
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185 #define ADC_Channel_11 ((uint8_t)0x0B)
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186 #define ADC_Channel_12 ((uint8_t)0x0C)
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187 #define ADC_Channel_13 ((uint8_t)0x0D)
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188 #define ADC_Channel_14 ((uint8_t)0x0E)
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189 #define ADC_Channel_15 ((uint8_t)0x0F)
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190 #define ADC_Channel_16 ((uint8_t)0x10)
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191 #define ADC_Channel_17 ((uint8_t)0x11)
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192
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193 #define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
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194 #define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
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195
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196 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
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197 ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
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198 ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
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199 ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
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200 ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
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201 ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
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202 ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
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203 ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
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204 ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
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205 /**
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206 * @}
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207 */
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208
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209 /** @defgroup ADC_sampling_time
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210 * @{
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211 */
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212
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213 #define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
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214 #define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
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215 #define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
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216 #define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
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217 #define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
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218 #define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
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219 #define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
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220 #define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
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221 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
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222 ((TIME) == ADC_SampleTime_7Cycles5) || \
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diff changeset
223 ((TIME) == ADC_SampleTime_13Cycles5) || \
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224 ((TIME) == ADC_SampleTime_28Cycles5) || \
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diff changeset
225 ((TIME) == ADC_SampleTime_41Cycles5) || \
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226 ((TIME) == ADC_SampleTime_55Cycles5) || \
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227 ((TIME) == ADC_SampleTime_71Cycles5) || \
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diff changeset
228 ((TIME) == ADC_SampleTime_239Cycles5))
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diff changeset
229 /**
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230 * @}
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231 */
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232
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diff changeset
233 /** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
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234 * @{
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235 */
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236
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diff changeset
237 #define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
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238 #define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
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239 #define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
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240 #define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
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241 #define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
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242
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243 #define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */
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244 #define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */
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245 #define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */
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246
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247 #define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */
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248 #define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */
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249 #define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */
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250 #define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */
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251 #define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */
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252
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253 #define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
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254 ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
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diff changeset
255 ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
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diff changeset
256 ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
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diff changeset
257 ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
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diff changeset
258 ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
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diff changeset
259 ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
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260 ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
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diff changeset
261 ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
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diff changeset
262 ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
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diff changeset
263 ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
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diff changeset
264 ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
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diff changeset
265 ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
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diff changeset
266 /**
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diff changeset
267 * @}
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diff changeset
268 */
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269
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diff changeset
270 /** @defgroup ADC_injected_channel_selection
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diff changeset
271 * @{
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272 */
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273
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274 #define ADC_InjectedChannel_1 ((uint8_t)0x14)
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275 #define ADC_InjectedChannel_2 ((uint8_t)0x18)
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276 #define ADC_InjectedChannel_3 ((uint8_t)0x1C)
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277 #define ADC_InjectedChannel_4 ((uint8_t)0x20)
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278 #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
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279 ((CHANNEL) == ADC_InjectedChannel_2) || \
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diff changeset
280 ((CHANNEL) == ADC_InjectedChannel_3) || \
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diff changeset
281 ((CHANNEL) == ADC_InjectedChannel_4))
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
282 /**
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
283 * @}
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
284 */
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
285
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
286 /** @defgroup ADC_analog_watchdog_selection
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diff changeset
287 * @{
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diff changeset
288 */
c59513fd84fb Initial commit of STM32 test code.
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289
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290 #define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
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291 #define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
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292 #define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
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293 #define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
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294 #define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
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295 #define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
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296 #define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
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297
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298 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
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299 ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
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300 ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
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301 ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
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302 ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
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303 ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
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diff changeset
304 ((WATCHDOG) == ADC_AnalogWatchdog_None))
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
305 /**
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
306 * @}
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
307 */
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
308
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
309 /** @defgroup ADC_interrupts_definition
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diff changeset
310 * @{
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parents:
diff changeset
311 */
c59513fd84fb Initial commit of STM32 test code.
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312
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diff changeset
313 #define ADC_IT_EOC ((uint16_t)0x0220)
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314 #define ADC_IT_AWD ((uint16_t)0x0140)
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diff changeset
315 #define ADC_IT_JEOC ((uint16_t)0x0480)
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316
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317 #define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
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318
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diff changeset
319 #define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
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320 ((IT) == ADC_IT_JEOC))
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
321 /**
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
322 * @}
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
323 */
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
324
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
325 /** @defgroup ADC_flags_definition
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
326 * @{
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parents:
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327 */
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
328
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diff changeset
329 #define ADC_FLAG_AWD ((uint8_t)0x01)
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diff changeset
330 #define ADC_FLAG_EOC ((uint8_t)0x02)
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diff changeset
331 #define ADC_FLAG_JEOC ((uint8_t)0x04)
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diff changeset
332 #define ADC_FLAG_JSTRT ((uint8_t)0x08)
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diff changeset
333 #define ADC_FLAG_STRT ((uint8_t)0x10)
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diff changeset
334 #define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
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335 #define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
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336 ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
337 ((FLAG) == ADC_FLAG_STRT))
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
338 /**
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
339 * @}
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
340 */
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
341
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
342 /** @defgroup ADC_thresholds
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
343 * @{
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
344 */
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345
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diff changeset
346 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
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347
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
348 /**
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
349 * @}
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
350 */
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
351
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
352 /** @defgroup ADC_injected_offset
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
353 * @{
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
354 */
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
355
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
356 #define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
357
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
358 /**
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
359 * @}
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
360 */
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
361
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
362 /** @defgroup ADC_injected_length
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
363 * @{
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
364 */
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
365
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
366 #define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
367
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
368 /**
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
369 * @}
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
370 */
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
371
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
372 /** @defgroup ADC_injected_rank
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
373 * @{
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
374 */
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
375
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
376 #define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
377
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
378 /**
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
379 * @}
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
380 */
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
381
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
382
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
383 /** @defgroup ADC_regular_length
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
384 * @{
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
385 */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
386
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
387 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
388 /**
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
389 * @}
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
390 */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
391
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
392 /** @defgroup ADC_regular_rank
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
393 * @{
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
394 */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
395
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
396 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
397
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
398 /**
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
399 * @}
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
400 */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
401
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
402 /** @defgroup ADC_regular_discontinuous_mode_number
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
403 * @{
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
404 */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
405
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
406 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
407
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
408 /**
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
409 * @}
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
410 */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
411
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
412 /**
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
413 * @}
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
414 */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
415
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
416 /** @defgroup ADC_Exported_Macros
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
417 * @{
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
418 */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
419
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
420 /**
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
421 * @}
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
422 */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
423
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
424 /** @defgroup ADC_Exported_Functions
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
425 * @{
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
426 */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
427
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
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428 void ADC_DeInit(ADC_TypeDef* ADCx);
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429 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
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430 void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
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431 void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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432 void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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433 void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
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434 void ADC_ResetCalibration(ADC_TypeDef* ADCx);
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435 FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
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436 void ADC_StartCalibration(ADC_TypeDef* ADCx);
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437 FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
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438 void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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439 FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
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440 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
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441 void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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442 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
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443 void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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444 uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
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445 uint32_t ADC_GetDualModeConversionValue(void);
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446 void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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447 void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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448 void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
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449 void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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450 void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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451 FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
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452 void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
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453 void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
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454 void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
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455 uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
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456 void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
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457 void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
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458 void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
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459 void ADC_TempSensorVrefintCmd(FunctionalState NewState);
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460 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
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461 void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
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462 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
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463 void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
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464
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465 #ifdef __cplusplus
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466 }
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467 #endif
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468
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469 #endif /*__STM32F10x_ADC_H */
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470
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471 /**
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472 * @}
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473 */
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474
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475 /**
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476 * @}
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477 */
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478
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479 /**
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480 * @}
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481 */
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482
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483 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/