annotate hw.c @ 49:ace431a0d0f5

Add SDIO code poached from STM. Use FatFS to read from SD card. LFN doesn't work reliably so it's disabled for now.
author Daniel O'Connor <darius@dons.net.au>
date Wed, 03 Apr 2013 23:34:20 +1030
parents 2db4bb90cfca
children bb52e6dad784
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1 #include <stdint.h>
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2 #include <stdio.h>
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3 #include "stm32f10x.h"
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5 #include "1wire.h"
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6 #include "lcd.h"
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7 #include "rtc.h"
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9 #define I2C_TIMEOUT 10000
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10 static void hw_port_cfg(void);
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12 void
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13 hw_init(void) {
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14 hw_port_cfg();
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15 lcd_init();
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16 lcd_setpwm(1000);
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17 }
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19 static void
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20 hw_port_cfg(void) {
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21 FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
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22 FSMC_NORSRAMTimingInitTypeDef p;
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23 GPIO_InitTypeDef GPIO_InitStructure;
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24 I2C_InitTypeDef I2C_InitStructure;
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25 SPI_InitTypeDef SPI_InitStructure;
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26 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
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27 USART_InitTypeDef USART_InitStructure;
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28
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29 /* Enable clocks */
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30 RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP | RCC_APB1Periph_TIM4 | RCC_APB1Periph_I2C1,
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31 ENABLE);
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32
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33 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOB |
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34 RCC_APB2Periph_GPIOE | RCC_APB2Periph_SPI1, ENABLE);
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36 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC | RCC_AHBPeriph_CRC, ENABLE);
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38 /* Allow access to BKP Domain */
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39 PWR_BackupAccessCmd(ENABLE);
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40
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41 /* Reset Backup Domain
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42 *
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43 * This resets the RTC etc back to 0 so probably only useful under user command
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44 BKP_DeInit();
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45 */
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46
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47 /* Enable Low Speed External clock */
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48 RCC_LSEConfig(RCC_LSE_ON);
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50 /* Wait till LSE is ready */
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51 while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)
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52 ;
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53
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54 /* Select LSE as RTC Clock Source */
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55 RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
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56
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57 /* Enable RTC Clock */
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58 RCC_RTCCLKCmd(ENABLE);
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59
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60 /* Wait for RTC registers synchronization */
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61 RTC_WaitForSynchro();
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62
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63 /* Wait until last write operation on RTC registers has finished */
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64 RTC_WaitForLastTask();
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65
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66 /* Wait until last write operation on RTC registers has finished */
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67 RTC_WaitForLastTask();
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68
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69 /* Set RTC prescaler: set RTC period to 1sec */
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70 RTC_SetPrescaler(RTC_PRESCALE);
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71
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72 /* Wait until last write operation on RTC registers has finished */
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73 RTC_WaitForLastTask();
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74
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75 /* Port configuration */
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76 /* Configure USART1 TX (PA.09) as alternate function push-pull */
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77 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
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78 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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79 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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80 GPIO_Init(GPIOA, &GPIO_InitStructure);
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81
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82 /* Configure USART1 RX (PA.10) as input floating */
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83 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
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84 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
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85 GPIO_Init(GPIOA, &GPIO_InitStructure);
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86
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87 /* Configure PB5 as output push-pull for LED */
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88 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
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89 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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90 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
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91 GPIO_Init(GPIOB, &GPIO_InitStructure);
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92
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93 /* Configure PB15 as input pull-up push-pull for push button */
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94 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
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95 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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96 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
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97 GPIO_Init(GPIOB, &GPIO_InitStructure);
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98
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99 /* USART configuration */
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100 /* USART1 - 115200 8n1, no flow control TX & RX enabled */
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101 USART_InitStructure.USART_BaudRate = 115200;
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102 USART_InitStructure.USART_WordLength = USART_WordLength_8b;
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103 USART_InitStructure.USART_StopBits = USART_StopBits_1;
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104 USART_InitStructure.USART_Parity = USART_Parity_No;
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105 USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
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106 USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
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107 USART_Init(USART1, &USART_InitStructure);
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108
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109 /* Enable interrupts on receive data */
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110 USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);
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111
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112 /* Enable USART */
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113 USART_Cmd(USART1, ENABLE);
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114
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115 /* Enable FSMC clock */
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116
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117 /* Configures LCD Control lines (FSMC Pins) in alternate function Push-Pull mode.
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118 *
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119 * PD0(D2), PD1(D3), PD4(NOE), PD5(NWE), PD7(NE1/CS), PD8(D13), PD9(D14),
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120 * PD10(D15), PD11(A16/RS) PD14(D0), PD15(D1)
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121 */
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122 GPIO_InitStructure.GPIO_Pin = (GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_7 |
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123 GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 |
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124 GPIO_Pin_14 | GPIO_Pin_15);
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125 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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126 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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127 GPIO_Init(GPIOD, &GPIO_InitStructure);
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128
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129 /* PE7(D4), PE8(D5), PE9(D6), PE10(D7), PE11(D8), PE12(D9), PE13(D10),
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130 * PE14(D11), PE15(D12)
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131 */
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132 GPIO_InitStructure.GPIO_Pin = (GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
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133 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
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134 GPIO_Pin_15);
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135 GPIO_Init(GPIOE, &GPIO_InitStructure);
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136
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137 /* Configure backlight control (PD13/FSMC_A18 remapped to TIM4_CH2) */
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138
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139 /* Enable timer function
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140 * Note source clock is SYSCLK / 2 = 36MHz
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141 */
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142 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13;
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143 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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144 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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145 GPIO_Init(GPIOD, &GPIO_InitStructure);
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146
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147 /* Remap TIM4_CH2 to PD13 */
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148 GPIO_PinRemapConfig(GPIO_Remap_TIM4, ENABLE);
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149
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150 /* Reset TIM4 */
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151 TIM_DeInit(TIM4);
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152
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153 /* Time Base configuration */
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154 TIM_TimeBaseStructure.TIM_Period = 999;
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155 TIM_TimeBaseStructure.TIM_Prescaler = 0;
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156 TIM_TimeBaseStructure.TIM_ClockDivision = 0;
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157 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Down;
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158
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159 TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
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160
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161 /* Enable timer */
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162 TIM_OC2PreloadConfig(TIM4, TIM_OCPreload_Enable);
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163 TIM_ARRPreloadConfig(TIM4, ENABLE);
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164 TIM_Cmd(TIM4, ENABLE);
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165
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166 /* Configure reset pin (PE1) as GPIO out PP */
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167 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;
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168 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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169 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
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170 GPIO_Init(GPIOE, &GPIO_InitStructure);
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171
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172 /* Configures the Parallel interface (FSMC) for LCD (Parallel mode) */
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173 /* Timing configuration */
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174 p.FSMC_AddressSetupTime = 5;
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175 p.FSMC_AddressHoldTime = 5;
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176 p.FSMC_DataSetupTime = 5;
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177 p.FSMC_BusTurnAroundDuration = 0;
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178 p.FSMC_CLKDivision = 0;
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179 p.FSMC_DataLatency = 0;
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180 p.FSMC_AccessMode = FSMC_AccessMode_A;
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181
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182 /* FSMC_Bank1_NORSRAM1 configured as follows:
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183 - Data/Address MUX = Disable
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184 - Memory Type = SRAM
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185 - Data Width = 16bit
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186 - Write Operation = Enable
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187 - Extended Mode = Disable
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188 - Asynchronous Wait = Disable */
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189 FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM1;
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190 FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
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191 FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
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192 FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
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193 FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
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194 FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
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195 FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
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196 FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
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197 FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
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198 FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
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199 FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
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200 FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
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201 FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
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202 FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
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203 FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
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204 FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
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205
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206 /* Enable FSMC_Bank1_NORSRAM1 */
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207 FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE);
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208
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209 /* Configure touch screen controller
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210 *
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211 * Connected to SPI1 which is shared with the AT45DB161D.
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212 *
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213 * The touch screen is selected with PB7.
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214 * The flash chip is selected with PA4.
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215 */
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216
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217 /* Configure MOSI, MISO and SCLK as alternate function PP */
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218 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
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219 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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220 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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221 GPIO_Init(GPIOA, &GPIO_InitStructure);
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222
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223 /* Configure flash chip select pin (PA4) as GPIO out PP */
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224 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
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225 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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226 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
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227 GPIO_Init(GPIOA, &GPIO_InitStructure);
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228
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229 /* Configure touch chip select pin (PB7) as GPIO out PP */
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230 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
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231 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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232 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
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233 GPIO_Init(GPIOB, &GPIO_InitStructure);
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234
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235 /* De-select touch & flash */
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236 GPIO_SetBits(GPIOA, GPIO_Pin_4);
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237 GPIO_SetBits(GPIOB, GPIO_Pin_7);
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238
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239 /* SPI1 Config */
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240 SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
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241 SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
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242 SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
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243 SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
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244 SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
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245 SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
24
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246 SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
8
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247 SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
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248 SPI_InitStructure.SPI_CRCPolynomial = 7;
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249 SPI_Init(SPI1, &SPI_InitStructure);
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250
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251 /* SPI1 enable */
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252 SPI_Cmd(SPI1, ENABLE);
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253
31
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254 /* Setup GPIO for delay test (2) 1-wire (3) & temp ctrl (4/5)
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255 * PE2 -> 3 (on header)
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256 * PE3 -> 4
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257 * PE4 -> 5
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258 * PE5 -> 6
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259 */
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260 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5;
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261 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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262 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
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263 GPIO_Init(GPIOE, &GPIO_InitStructure);
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264
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265 /* Setup 1-wire bus */
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266 OWInit();
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267
18
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268 /* Setup I2C bus */
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269
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270 /* Configure SCL/SDA pins */
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271 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9;
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272 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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273 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
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274 GPIO_Init(GPIOB, &GPIO_InitStructure);
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275
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276 /* Reset I2C1 */
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277 I2C_DeInit(I2C1);
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278
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279 /* Setup I2C1 */
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280 I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
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281 I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
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282 I2C_InitStructure.I2C_OwnAddress1 = 0x00;
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283 I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
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284 I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
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285 I2C_InitStructure.I2C_ClockSpeed = 100000;
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286 I2C_Init(I2C1, &I2C_InitStructure);
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287
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288 /* Start I2C controller */
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289 I2C_Cmd(I2C1, ENABLE);
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290
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291 /* Enable debug block for cycle counter
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292 * From http://forums.arm.com/index.php?/topic/13949-cycle-count-in-cortex-m3/
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293 * via http://stackoverflow.com/questions/11530593/cycle-counter-on-arm-cortex-m4-or-m3/11530829#11530829
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294 */
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295 volatile uint32_t *DWT_CONTROL = (uint32_t *)0xe0001000;
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296 volatile uint32_t *SCB_DEMCR = (uint32_t *)0xe000edfc;
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297
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298 *SCB_DEMCR = *SCB_DEMCR | 0x01000000;
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299 *DWT_CONTROL = *DWT_CONTROL | 1 ; // enable the counter
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300
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301 /* Setup SDIO
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302 * See SD_LowLevelInit from libs/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c
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303 */
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304
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305 /* GPIOC and GPIOD Periph clock enable */
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306 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD, ENABLE);
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307
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308 /* Configure SDIO pins for AF
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309 PC8 -> SD0
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310 PC9 -> SD1
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311 PC10 -> SD2
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312 PC11 -> SD3
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313 PC12 -> SCK
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314 */
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315 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
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316 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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317 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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318 GPIO_Init(GPIOC, &GPIO_InitStructure);
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319
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320 /* Configure PD2 -> CMD SDIO pin for AF */
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321 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
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322 GPIO_Init(GPIOD, &GPIO_InitStructure);
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323
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324 /* Enable the SDIO AHB Clock */
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325 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_SDIO, ENABLE);
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326
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327 /* Enable the DMA2 Clock */
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328 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE);
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329 }