Mercurial > ~darius > hgwebdir.cgi > stm32temp
annotate delay.c @ 70:aaf0603d7f88
Add routine to CRC a block of flash. Use it to verify a flash block write.
author | Daniel O'Connor <darius@dons.net.au> |
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date | Sun, 14 Apr 2013 22:53:50 +0930 |
parents | a38003b97de6 |
children | cecb0506f4b8 |
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Use debug cycle counter to handle delays.
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1 #include <assert.h> |
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2 #include <stdint.h> |
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3 #include "stm32f10x.h" |
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4 #include "delay.h" |
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5 |
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6 /* Sleep for nCount usec |
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7 */ |
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8 void |
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9 delay(uint32_t nCount) { |
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10 uint32_t dly, cnt, clk_per_usec, max_dly; |
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11 volatile uint32_t *DWT_CYCCNT = (uint32_t *)0xe0001004; |
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12 |
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13 __disable_irq(); |
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15 #ifdef SYSCLK_FREQ_72MHz |
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16 clk_per_usec = 72; |
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17 max_dly = (1<<31) / clk_per_usec; /* Really half the maximum (still ~30 seconds at 72MHz) */ |
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18 #else |
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19 #error "Unknown clock frequency" |
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20 #endif |
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21 assert(nCount < max_dly); |
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22 |
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23 cnt = *DWT_CYCCNT; /* Get current cycle count */ |
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24 dly = nCount * clk_per_usec; |
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25 dly += cnt; /* Compute cycle count to stop at */ |
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26 if (dly < cnt) |
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27 /* Stop count wrapped, wait until the counter wraps around */ |
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28 while (*DWT_CYCCNT > cnt) |
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29 ; |
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30 /* Wait until we get to the stop count */ |
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31 while (*DWT_CYCCNT < dly) |
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32 ; |
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33 |
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34 __enable_irq(); |
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35 } |
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36 |