annotate flash.c @ 28:7f8e5780024b

- Add depend target. - Switch to Homebrew toolchain
author Daniel O'Connor <darius@dons.net.au>
date Tue, 27 Nov 2012 13:16:47 +1030
parents 5c9d2e3d6591
children 03592ca4d37e
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1 #include <stdio.h>
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2 #include <stdint.h>
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3 #include <string.h>
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4 #include <stdlib.h>
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5 #include <assert.h>
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6
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7 #include "stm32f10x.h"
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8 #include "spi.h"
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9 #include "flash.h"
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10
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11 #define FL_SELECT() GPIO_ResetBits(GPIOA, GPIO_Pin_4)
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12 #define FL_DESELECT() GPIO_SetBits(GPIOA, GPIO_Pin_4)
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14 static const char *flstattbl[] = {
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15 "BUSY",
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16 "WEL",
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17 "BP0",
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18 "BP1",
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19 "BP2",
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20 "BP3",
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21 "AAI",
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22 "BPL"
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23 };
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24
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25 #define RW_IDLE 0
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26 #define RW_RUNNING 1
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28 /* Holds all the settings needed */
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29 typedef struct {
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30 uint8_t fermenter_ROM[8];
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31 uint8_t fridge_ROM[8];
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32 uint8_t ambient_ROM[8];
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33 int16_t target_temp;
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34 uint16_t hysteresis;
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35 /* How much to under/overshoot on heating/cooling */
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36 int16_t minheatovershoot;
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37 int16_t mincoolovershoot;
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38
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39 /* Minimum time the cooler can be on/off */
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40 int16_t mincoolontime;
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41 int16_t mincoolofftime;
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42
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43 /* Minimum time the heater can be on/off */
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44 int16_t minheatontime;
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45 int16_t minheatofftime;
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46
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47 #define TC_MODE_AUTO 'a' /* Automatic control */
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48 #define TC_MODE_HEAT 'h' /* Force heating */
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49 #define TC_MODE_COOL 'c' /* Force cooling */
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50 #define TC_MODE_IDLE 'i' /* Force idle */
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51 #define TC_MODE_NOTHING 'n' /* Do nothing (like idle but log nothing) */
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52 char mode;
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53
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54 /* Bit patterns for various modes */
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55 uint8_t coolbits;
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56 uint8_t heatbits;
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57 uint8_t idlebits;
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58
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59 /* Check/stale times */
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60 int16_t check_interval;
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61 int16_t stale_factor;
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62
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63 /* Beep if stale */
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64 int8_t dobeep;
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65
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66 /* Pad to 4 bytes */
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67 uint8_t pad[1];
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68
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69 } __attribute__((packed, aligned(4))) settings_t;
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70
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71 const settings_t default_settings = {
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72 .fermenter_ROM = { 0x10, 0x4c, 0x7d, 0x53, 0x01, 0x08, 0x00, 0xff },
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73 .fridge_ROM = { 0x10, 0x6f, 0x40, 0x53, 0x01, 0x08, 0x00, 0x16 },
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74 .ambient_ROM = { 0x10, 0x76, 0x05, 0x53, 0x01, 0x08, 0x00, 0x8c },
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75 .target_temp = 1000,
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76 .hysteresis = 100,
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77 .minheatovershoot = 50,
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78 .mincoolovershoot = -50,
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79 .mincoolontime = 300,
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80 .mincoolofftime = 600,
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81 .minheatontime = 60,
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82 .minheatofftime = 60,
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83 .mode = TC_MODE_AUTO,
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84 .coolbits = 1 << 6,
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85 .heatbits = 1<< 7,
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86 .idlebits = 0x00,
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87 .check_interval = 10,
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88 .stale_factor = 3,
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89 .dobeep = 0
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90 };
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91
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92 /* RAM copy of setting */
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93 static settings_t ram_settings;
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94
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95 static int writestate = RW_IDLE;
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96 static int readstate = RW_IDLE;
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97
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98 void
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99 flashcmd(char **argv, int argc) {
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100 uint8_t status, tmp, len;
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101 uint32_t addr;
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102
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103 if (argc == 0) {
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104 fputs("No command specified\r\n", stdout);
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105 return;
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106 }
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107
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108 if (!strcmp(argv[0], "str")) {
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109 status = flashreadstatus();
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110 fputs("Status = ", stdout);
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111 for (unsigned int i = 0; i < sizeof(flstattbl) / sizeof(flstattbl[0]); i++)
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112 if (status & 1 << i) {
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113 fputs(flstattbl[i], stdout);
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114 fputs(" ", stdout);
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115 }
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116 printf("(0x%02x)\r\n", status);
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117 } else if (!strcmp(argv[0], "stw")) {
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118 if (argc != 2) {
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119 fputs("Incorrect number of arguments\r\n", stdout);
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120 return;
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121 }
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122 tmp = atoi(argv[1]);
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123 flashwritestatus(tmp);
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124 status = flashreadstatus();
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125 printf("Wrote 0x%02x to status, now 0x%02x\r\n", tmp, status);
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126 } else if (!strcmp(argv[0], "er")) {
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127 if (argc != 2) {
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128 fputs("Incorrect number of arguments\r\n", stdout);
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diff changeset
129 return;
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diff changeset
130 }
26
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diff changeset
131 addr = atoi(argv[1]);
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diff changeset
132 flash4kerase(addr);
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diff changeset
133 printf("Erased 0x%x\r\n", (unsigned int)addr);
21
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134 } else if (!strcmp(argv[0], "rd")) {
27
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parents: 26
diff changeset
135 if (argc < 2) {
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diff changeset
136 fputs("Incorrect number of arguments\r\n", stdout);
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parents: 26
diff changeset
137 return;
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parents: 26
diff changeset
138 }
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parents: 26
diff changeset
139
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diff changeset
140 addr = atoi(argv[1]);
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diff changeset
141
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diff changeset
142 if (argc > 2)
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diff changeset
143 len = atoi(argv[2]);
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diff changeset
144 else
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diff changeset
145 len = 16;
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parents: 26
diff changeset
146
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diff changeset
147 flashstartread(addr);
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148
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diff changeset
149 for (uint32_t i = 0; i < len; i++)
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diff changeset
150 printf("Read 0x%02x from 0x%06x\r\n", flashreadbyte(), (unsigned int)(addr + i));
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diff changeset
151 flashstopread();
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diff changeset
152
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diff changeset
153 fputs("\r\n", stdout);
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154 } else if (!strcmp(argv[0], "wr")) {
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diff changeset
155 if (argc < 2) {
21
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156 fputs("Incorrect number of arguments\r\n", stdout);
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157 return;
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158 }
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159
26
74efdb21ae5d Use a 32 bit var to hold address from atoi().
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diff changeset
160 addr = atoi(argv[1]);
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diff changeset
161
27
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diff changeset
162 if (argc > 2)
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diff changeset
163 len = atoi(argv[2]);
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diff changeset
164 else
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diff changeset
165 len = 16;
21
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166
25
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167 for (int i = 0; i < 16; i += 2) {
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diff changeset
168 uint16_t data;
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diff changeset
169 data = ((i + 1) << 8) | i;
26
74efdb21ae5d Use a 32 bit var to hold address from atoi().
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diff changeset
170 printf("Writing 0x%04x to 0x%06x\r\n", data, (unsigned int)(addr + i));
25
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diff changeset
171
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diff changeset
172 if (i == 0)
26
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diff changeset
173 flashstartwrite(addr, data);
25
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diff changeset
174 else
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diff changeset
175 flashwriteword(data);
21
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diff changeset
176 }
25
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diff changeset
177 flashstopwrite();
27
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diff changeset
178 } else if (!strcmp(argv[0], "tw")) {
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diff changeset
179 /* Copy default to RAM */
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diff changeset
180 bcopy(&default_settings, &ram_settings, sizeof(default_settings));
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diff changeset
181
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diff changeset
182 /* Write RAM copy into flash */
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183 flashwriteblock(0, sizeof(ram_settings), &ram_settings);
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184 } else if (!strcmp(argv[0], "tr")) {
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diff changeset
185 int crcok;
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diff changeset
186
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diff changeset
187 /* Read flash copy to RAM */
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diff changeset
188 crcok = flashreadblock(0, sizeof(ram_settings), &ram_settings);
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diff changeset
189
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diff changeset
190 printf("CRC is %s\r\n", crcok ? "OK" : "bad");
21
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191 } else if (!strcmp(argv[0], "id")) {
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diff changeset
192 printf("Flash ID = 0x%04hx (expect 0xbf41)\r\n", flashreadid());
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193 } else {
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diff changeset
194 fputs("Unknown sub command\r\n", stdout);
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195 return;
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diff changeset
196 }
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diff changeset
197 }
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diff changeset
198
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diff changeset
199 void
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diff changeset
200 flash4kerase(uint32_t addr) {
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diff changeset
201 flashenablewrite(); /* Enable writing */
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diff changeset
202
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diff changeset
203 FL_SELECT(); /* Select device */
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diff changeset
204
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diff changeset
205 SPI_WriteByte(FL_4KERASE); /* Send command */
25
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diff changeset
206 SPI_WriteByte(addr >> 16); /* Send address */
a9cc07caa801 Add stream read/write commands.
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diff changeset
207 SPI_WriteByte(addr >> 8);
a9cc07caa801 Add stream read/write commands.
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diff changeset
208 SPI_WriteByte(addr);
21
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diff changeset
209
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diff changeset
210 FL_DESELECT();
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diff changeset
211
27
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diff changeset
212 //fputs("4k erase ", stdout);
25
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diff changeset
213 flashwait();
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parents: 21
diff changeset
214 }
a9cc07caa801 Add stream read/write commands.
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parents: 21
diff changeset
215
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parents: 21
diff changeset
216 void
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Daniel O'Connor <darius@dons.net.au>
parents: 21
diff changeset
217 flashwait(void) {
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parents: 21
diff changeset
218 uint8_t cnt;
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parents: 21
diff changeset
219
21
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220 /* Wait for not BUSY */
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diff changeset
221 for (cnt = 0; (flashreadstatus() & FL_BUSY) != 0; cnt++)
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parents: 8
diff changeset
222 ;
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diff changeset
223
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diff changeset
224 //printf("cnt = %d\r\n", cnt);
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diff changeset
225 }
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diff changeset
226
8
58d76cf522ff Split out code into separate files.
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parents:
diff changeset
227 uint16_t
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parents:
diff changeset
228 flashreadid(void) {
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parents:
diff changeset
229 uint8_t fac, dev;
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parents:
diff changeset
230
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parents:
diff changeset
231 FL_SELECT(); /* Select device */
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parents:
diff changeset
232
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parents:
diff changeset
233 SPI_WriteByte(FL_RDID); /* Send command */
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parents:
diff changeset
234 SPI_WriteByte(0x00); /* Send address cycles (ID data starts at 0) */
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parents:
diff changeset
235 SPI_WriteByte(0x00);
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parents:
diff changeset
236 SPI_WriteByte(0x00);
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parents:
diff changeset
237 fac = SPI_WriteByte(0x00); /* Read ID */
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parents:
diff changeset
238 dev = SPI_WriteByte(0x00);
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parents:
diff changeset
239
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parents:
diff changeset
240 FL_DESELECT(); /* De-select device */
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parents:
diff changeset
241
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parents:
diff changeset
242 return fac << 8 | dev;
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parents:
diff changeset
243 }
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parents:
diff changeset
244
21
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parents: 8
diff changeset
245 void
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diff changeset
246 flashenablewrite(void) {
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parents: 8
diff changeset
247 FL_SELECT(); /* Select device */
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diff changeset
248
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diff changeset
249 SPI_WriteByte(FL_WREN); /* Send command */
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parents: 8
diff changeset
250
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diff changeset
251 FL_DESELECT(); /* De-select device */
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diff changeset
252 }
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diff changeset
253
8
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parents:
diff changeset
254 uint8_t
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parents:
diff changeset
255 flashreadstatus(void) {
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parents:
diff changeset
256 uint8_t status;
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parents:
diff changeset
257
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parents:
diff changeset
258 FL_SELECT(); /* Select device */
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parents:
diff changeset
259
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parents:
diff changeset
260 SPI_WriteByte(FL_RDSR); /* Send command */
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parents:
diff changeset
261 SPI_WriteByte(0x00); /* Send dummy byte for address cycle */
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parents:
diff changeset
262 status = SPI_WriteByte(0x00); /* Read status */
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parents:
diff changeset
263
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parents:
diff changeset
264 FL_DESELECT(); /* De-select device */
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parents:
diff changeset
265
58d76cf522ff Split out code into separate files.
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parents:
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266 return status;
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267 }
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268
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269 void
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270 flashwritestatus(uint8_t status) {
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271 /* Enable status write */
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272 FL_SELECT(); /* Select device */
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273 SPI_WriteByte(FL_EWSR); /* Send command */
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274 SPI_WriteByte(0x00); /* Send data byte */
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275 FL_DESELECT();
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276
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277 /* Actually write status */
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278 FL_SELECT(); /* Re-select device for new command */
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279 SPI_WriteByte(FL_WRSR); /* Send command */
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280 SPI_WriteByte(status); /* Send data byte */
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281 FL_DESELECT(); /* De-select device */
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282 }
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283
21
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284 uint8_t
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285 flashread(uint32_t addr) {
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286 uint8_t data;
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287
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288 FL_SELECT(); /* Select device */
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289
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290 SPI_WriteByte(FL_READ); /* Send command */
25
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291 SPI_WriteByte(addr >> 16); /* Send address */
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292 SPI_WriteByte(addr >> 8);
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293 SPI_WriteByte(addr);
21
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294 data = SPI_WriteByte(0x00); /* Read data */
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295
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296 FL_DESELECT(); /* De-select device */
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297
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298 return data;
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299 }
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300
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301 void
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302 flashwrite(uint32_t addr, uint8_t data) {
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303 flashwait();
21
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304 flashenablewrite(); /* Enable writes */
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305
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306 FL_SELECT(); /* Select device */
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307
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308 SPI_WriteByte(FL_BYTEPROG); /* Send command */
25
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309 SPI_WriteByte(addr >> 16); /* Send address */
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310 SPI_WriteByte(addr >> 8);
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311 SPI_WriteByte(addr);
21
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312 SPI_WriteByte(data); /* Write data */
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313
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314 FL_DESELECT(); /* De-select device */
25
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315
21
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316 }
25
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317
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318 /*
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319 * fStream reading looks like so
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320 *
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321 */
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322
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323 void
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324 flashstartread(uint32_t addr) {
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325 assert(readstate == RW_IDLE);
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326
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327 FL_SELECT(); /* Select device */
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328
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329 SPI_WriteByte(FL_READ); /* Send command */
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330 SPI_WriteByte(addr >> 16); /* Send address */
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331 SPI_WriteByte(addr >> 8);
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332 SPI_WriteByte(addr);
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333
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334 readstate = RW_RUNNING;
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335 }
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336
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337 uint8_t
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338 flashreadbyte(void) {
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339 assert(readstate == RW_RUNNING);
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340 return SPI_WriteByte(0x00); /* Read data */
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341 }
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342
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343 void
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344 flashstopread(void) {
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345 assert(readstate == RW_RUNNING);
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346
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347 FL_DESELECT();
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348
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349 readstate = RW_IDLE;
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350 }
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351
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352 /*
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353 * Auto increment writing looks like so
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354 *
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355 * Enable writing CS, WREN, nCS
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356 * Send start address & first data word CS, AAI + addr + data, nCS
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357 * Send subsequent words wait for nBUSY, CS, AAI + data, nCS
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358 * ...
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359 * Disable writing CS, WRDI, nCS
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360 *
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361 * XXX: EBSY command links SO to flash busy state, I don't think the
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362 * STM32 could sample it without switching out of SPI mode.
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363 */
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364 void
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365 flashstartwrite(uint32_t addr, uint16_t data) {
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366 assert(writestate == RW_IDLE);
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367
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368 flashenablewrite(); /* Enable writes */
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369
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370 FL_SELECT(); /* Select device */
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371
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372 SPI_WriteByte(FL_AAIWP); /* Send command */
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373 SPI_WriteByte(addr >> 16);
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374 SPI_WriteByte(addr >> 8);
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375 SPI_WriteByte(addr & 0xff); /* Send address */
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376
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377 SPI_WriteByte(data & 0xff); /* Write LSB */
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378 SPI_WriteByte(data >> 8); /* Write MSB */
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379
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380 FL_DESELECT();
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381
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382 writestate = RW_RUNNING;
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383 }
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384
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385 void
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386 flashwriteword(uint16_t data) {
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387 assert(writestate == RW_RUNNING);
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388
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389 //fputs("write word ", stdout);
25
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390 flashwait(); /* Wait until not busy */
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391
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392 FL_SELECT(); /* Select device */
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diff changeset
393
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394 SPI_WriteByte(FL_AAIWP); /* Send command */
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395 SPI_WriteByte(data & 0xff); /* Write LSB */
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396 SPI_WriteByte(data >> 8); /* Write MSB */
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diff changeset
397
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398 FL_DESELECT(); /* De-select device */
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399 }
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diff changeset
400
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diff changeset
401 void
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402 flashstopwrite(void) {
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403 assert(writestate == RW_RUNNING);
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diff changeset
404
27
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405 //fputs("flash stop write start ", stdout);
25
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406 flashwait(); /* Wait until not busy */
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diff changeset
407
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408 FL_SELECT(); /* Select device */
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diff changeset
409
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diff changeset
410 SPI_WriteByte(FL_WRDI); /* Send command */
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diff changeset
411
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diff changeset
412 FL_DESELECT(); /* Deselect device */
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diff changeset
413
27
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414 //fputs("flash stop write end ", stdout);
25
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diff changeset
415 flashwait(); /* Wait until not busy */
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diff changeset
416
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diff changeset
417 writestate = RW_IDLE;
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418 }
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419
27
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420 int
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421 flashreadblock(uint32_t addr, uint32_t len, void *_data) {
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422 uint8_t *data = _data;
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423 uint32_t flashcrc, ramcrc;
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424
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425 /* Must be a multiple of 4 due to CRC check */
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426 assert(len % 4 == 0);
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427
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428 flashstartread(addr);
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429 for (int i = len; i > 0; i--) {
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430 *data = flashreadbyte();
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431 data++;
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432 }
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433
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434 flashcrc = flashreadbyte();
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435 flashcrc |= flashreadbyte() << 8;
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436 flashcrc |= flashreadbyte() << 16;
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437 flashcrc |= flashreadbyte() << 24;
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438
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439 flashstopread();
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440
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441 /* Calculate CRC */
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442 CRC_ResetDR();
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443 ramcrc = CRC_CalcBlockCRC((uint32_t *)_data, len / 4);
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444
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445 printf("RAM CRC 0x%08x Flash CRC 0x%08x\r\n", (uint)ramcrc, (uint)flashcrc);
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446
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447 if (ramcrc == flashcrc)
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448 return 1;
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449 else
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450 return 0;
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451 }
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452
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453 void
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454 flashwriteblock(uint32_t addr, uint32_t len, void *_data) {
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455 uint16_t *data = _data;
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456 uint32_t crc;
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457
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458 printf("Writing %u bytes to 0x%06x\r\n", (uint)len, (uint)addr);
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diff changeset
459
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diff changeset
460 /* Ensure data is
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461 * - 16 bit aligned
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462 * - a multiple of 32 bits in length (for CRCs, the flash only need 16 bits)
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463 * - not longer than a sector
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464 */
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465 assert(addr % 2 == 0);
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466 assert(len % 4 == 0);
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467 assert(len <= 4096);
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468
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469 /* Disable write protect */
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diff changeset
470 flashwritestatus(0x00);
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diff changeset
471
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diff changeset
472 /* Erase sector */
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diff changeset
473 flash4kerase(addr);
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474
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475 /* Write data */
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diff changeset
476 for (uint i = 0; i < len / 2; i++) {
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diff changeset
477 if (i == 0)
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478 flashstartwrite(addr, *data);
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479 else
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480 flashwriteword(*data);
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481 data++;
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482 }
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diff changeset
483
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diff changeset
484 /* Calculate CRC */
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diff changeset
485 CRC_ResetDR();
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diff changeset
486 crc = CRC_CalcBlockCRC((uint32_t *)_data, len / 4);
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diff changeset
487
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488 printf("CRC is 0x%08x\r\n", (uint)crc);
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diff changeset
489
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diff changeset
490 /* Write CRC */
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diff changeset
491 flashwriteword(crc);
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diff changeset
492 flashwriteword(crc >> 16);
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diff changeset
493
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494 flashstopwrite();
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495 }