annotate lcd.c @ 4:2c87e30c982d

Add LCD init, touch screen writing etc.. PWM of LCD backlight doesn't work yet though..
author Daniel O'Connor <darius@dons.net.au>
date Tue, 03 Jan 2012 22:37:18 +1030
parents 74e9b3baac1e
children efa2c22266e3
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3
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1 /*
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2 * Example code (I think)
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3 * ~/projects/STM32Strive/奋斗STM32开发板例程/奋斗STM32开发板例程/奋斗STM32开发板MINI/STM32奋斗版ucOS II V2.86 uCGUI 3.9 DEMO-V2/STM32奋斗版ucOS II V2.86 uCGUI 3.9 DEMO
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4 *
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5 * Schematics
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6 * Main board ~/Downloads/Strive\ Mini\ STM32\ Schematic.pdf
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7 * LCD board ~/Downloads/Strive Mini LCD STM32 Schematic.pdf
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8 * MCU reference manual
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9 * ~/Downloads/CD00171190.pdf
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10 * MCU Data sheet (pinout)
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11 * ~/Downloads/CD00191185.pdf
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12 * LCD data sheet
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13 *
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14 */
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15 /* LCD board MCU
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16 1 VCC
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17 2 TC_SCK PA5/SPI1_SCK
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18 3 GND
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19 4 TC_CS PB7/SPI1_CS3
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20 5 RST PE1 FSMC_NBL1? (unlikely)
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21 6 TC_DIN PA7/SPI1_MOSI
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22 7 nOE PD4/FSMC_nOE
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23 8 TC_DOUT PA6/SPI1_MISO
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24 9 nWR PD5/FSMC_nWE
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25 10 TC_INT PB6
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26 11 CS PD7/FSMC_NE1/FSMC_NCE2
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27 12 NC
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28 13 RS PD11/FSMC_A16
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29 14 NC
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30 15 D7 PE10/FSMC_D7
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31 16 NC
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32 17 D6 PE9/FSMC_D6
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33 18 NC
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34 19 D3 PD1/FSMC_D3
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35 20 D13 PD8/FSMC_D13
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36 21 D5 PE8/FSMC_D5
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37 22 D12 PE15/FSMC_D12
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38 23 D4 PE7/FSMC_D4
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39 24 GND
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40 25 NC
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41 26 D11 PE14/FSMC_D11
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42 27 D2 PD0/FSMC_D2
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43 28 D10 PE13/FSMC_D10
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44 29 D1 PD15/FSMC_D1
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45 30 D9 PE12/FSMC_D9
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46 31 D0 PD14/FSMC_D0
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47 32 D14 PD9/FSMC_D9
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48 33 NC
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49 34 D8 PE11/FSMC_D8
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50 35 NC
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51 36 NC
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52 37 NC
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53 38 LCD_PWM PD13/TIM4_CH2
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54 39 NC
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55 40 D15 PD10/FSMC_D15
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56 */
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57
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58 #include <stdio.h>
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59 #include "stm32f10x.h"
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60 #include "lcd.h"
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61
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62 #define Bank1_LCD_C ((uint32_t)0x60000000) /* Register Address */
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63 #define Bank1_LCD_D ((uint32_t)0x60020000) /* Data Address */
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64
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65 unsigned long colour1 = 0;
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66
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67 void
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68 LCD_WR_Reg(uint16_t index, uint16_t val) {
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69 *(__IO uint16_t *)(Bank1_LCD_C) = index;
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70 *(__IO uint16_t *)(Bank1_LCD_D) = val;
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71 }
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72
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73 uint16_t
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74 LCD_RD_Reg(uint16_t index) {
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75 *(__IO uint16_t *)(Bank1_LCD_C) = index;
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76 return(*(__IO uint16_t *)(Bank1_LCD_D));
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77 }
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78
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79 uint16_t
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80 LCD_RD_Data(int first) {
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81 uint16_t a = 0;
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82 if (first)
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83 a = *(__IO uint16_t *) (Bank1_LCD_D); /* Dummy */
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84 a = *(__IO uint16_t *) (Bank1_LCD_D); /* Read */
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85
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86 return (a);
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87 }
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88
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89 void
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90 LCD_WR_Data(uint16_t val) {
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91 *(__IO uint16_t *)(Bank1_LCD_D) = val;
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92 }
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93
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94 /* Callers imply this is in milliseconds but that seems unlikely */
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95 void
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96 Delay(__IO uint32_t nCount) {
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97 for(; nCount != 0; nCount--)
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98 ;
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99 }
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100
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101 uint8_t
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102 SPI_WriteByte(uint8_t out) {
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103 uint8_t in = 0;
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104
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105 /* Wait until the transmit buffer is empty */
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106 while (SPI_I2S_GetFlagStatus(SPI1,SPI_I2S_FLAG_TXE) == RESET)
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107 ;
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108
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109 /* Send the byte */
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110 SPI_I2S_SendData(SPI1, out);
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111
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112 /* Wait until a data is received */
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113 while (SPI_I2S_GetFlagStatus(SPI1,SPI_I2S_FLAG_RXNE) == RESET)
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114 ;
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115
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116 /* Get the received data */
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117 in = SPI_I2S_ReceiveData(SPI1);
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118
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119 /* Return the shifted data */
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120 return (in);
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121 }
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122
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123 #define TP_SELECT() GPIO_ResetBits(GPIOB, GPIO_Pin_7)
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124 #define TP_DESELECT() GPIO_SetBits(GPIOB, GPIO_Pin_7)
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125 uint16_t
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126 TPRead(uint8_t type) {
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127 uint16_t x = 0;
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128
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129 /* Select device */
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130 TP_SELECT();
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131
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132 /* Do conversion */
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133 Delay(10);
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134 SPI_WriteByte(type);
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135
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136 /* Read result */
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137 Delay(10);
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138 x = SPI_WriteByte(0x00);
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139 x <<= 8;
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140 x |= SPI_WriteByte(0x00);
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141 Delay(10);
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142
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143 /* De-select device */
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144 TP_DESELECT();
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145
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146 /* Right justify 12 bit result */
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147 x = x >> 3;
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148 return (x);
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149 }
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150
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151 #define FL_SELECT() GPIO_ResetBits(GPIOA, GPIO_Pin_4)
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152 #define FL_DESELECT() GPIO_SetBits(GPIOA, GPIO_Pin_4)
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153
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154 #define FL_READ 0x03
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155 #define FL_HSREAD 0x0b
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156 #define FL_32KERASE 0x52
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157 #define FL_64KERASE 0xd8
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158 #define FL_CHIPERASE 0x60
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159 #define FL_BYTEPROG 0x02
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160 #define FL_AAIWP 0xad
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161 #define FL_RDSR 0x05
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162 #define FL_EWSR 0x50
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163 #define FL_WRSR 0x01
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164 #define FL_WREN 0x06
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165 #define FL_WRDI 0x04
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166 #define FL_RDID 0x90
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167 #define FL_JEDECID 0x9f
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168 #define FL_EBSY 0x70
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169 #define FL_DBSY 0x80
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170
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171 uint16_t
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172 FlashReadID(void) {
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173 uint8_t fac, dev;
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174
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175 FL_SELECT(); /* Select device */
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176
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177 SPI_WriteByte(FL_RDID); /* Send command */
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178 SPI_WriteByte(0x00); /* Send address cycles (ID data starts at 0) */
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179 SPI_WriteByte(0x00);
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180 SPI_WriteByte(0x00);
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181 fac = SPI_WriteByte(0x00); /* Read ID */
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182 dev = SPI_WriteByte(0x00);
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183
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184 FL_DESELECT(); /* De-select device */
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185
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186 return fac << 8 | dev;
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187 }
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188
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189 uint8_t
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190 FlashReadStatus(void) {
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191 uint8_t status;
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192
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193 FL_SELECT(); /* Select device */
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194
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195 SPI_WriteByte(FL_RDSR); /* Send command */
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196 SPI_WriteByte(0x00); /* Send dummy byte for address cycle */
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197 status = SPI_WriteByte(0x00); /* Read status */
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198
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199 FL_DESELECT(); /* De-select device */
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200
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201 return status;
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202 }
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203
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204 void
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205 FlashWriteStatus(uint8_t status) {
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206 /* Enable status write */
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207 FL_SELECT(); /* Select device */
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208 SPI_WriteByte(FL_EWSR); /* Send command */
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209 SPI_WriteByte(0x00); /* Send data byte */
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210 FL_DESELECT();
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211
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212 /* Actually write status */
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213 FL_SELECT(); /* Re-select device for new command */
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214 SPI_WriteByte(FL_WRSR); /* Send command */
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215 SPI_WriteByte(status); /* Send data byte */
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216 FL_DESELECT(); /* De-select device */
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217 }
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218
3
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219 void
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220 LCD_init(void) {
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221 GPIO_InitTypeDef GPIO_InitStructure;
4
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222 SPI_InitTypeDef SPI_InitStructure;
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223 FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
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224 FSMC_NORSRAMTimingInitTypeDef p;
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225 #if 0
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226 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
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227 TIM_OCInitTypeDef TIM_OCInitStructure;
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228 TIM_BDTRInitTypeDef TIM_BDTRInitStructure;
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229 #endif
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230 uint16_t id;
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231
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232 /* Enable FSMC clock */
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233 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
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234
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235 /* Enable GPIOD clock */
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236 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE);
3
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237
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238 /* Configures LCD Control lines (FSMC Pins) in alternate function Push-Pull mode.
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239 *
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240 * PD0(D2), PD1(D3), PD4(NOE), PD5(NWE), PD7(NE1/CS), PD8(D13), PD9(D14),
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241 * PD10(D15), PD11(A16/RS) PD14(D0), PD15(D1)
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242 */
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243 GPIO_InitStructure.GPIO_Pin = (GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_7 |
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244 GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_14 | GPIO_Pin_15);
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245 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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246 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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247 GPIO_Init(GPIOD, &GPIO_InitStructure);
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248
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249 /* PE7(D4), PE8(D5), PE9(D6), PE10(D7), PE11(D8), PE12(D9), PE13(D10),
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250 * PE14(D11), PE15(D12)
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251 */
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252 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
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253 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
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254 GPIO_Init(GPIOE, &GPIO_InitStructure);
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255
4
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256 /* Configure backlight control (PD13/FSMC_A18 remapped to TIM4_CH2) */
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257 #if 0
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258 /* Enable TIM4 clock */
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259 RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
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260
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261 /* Enable timer function */
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262 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13;
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263 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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264 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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265 GPIO_Init(GPIOD, &GPIO_InitStructure);
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266
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267 /* Remap TIM4_CH2 to PD13 */
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268 GPIO_PinRemapConfig(GPIO_Remap_TIM4, ENABLE);
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269
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270 /* Reset TIM4 */
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271 TIM_DeInit(TIM4);
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272
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273 /* Time Base configuration */
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274 TIM_TimeBaseStructure.TIM_Prescaler = 0x00;
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275 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
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276 TIM_TimeBaseStructure.TIM_Period = 0x8000;
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277 TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;
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278 TIM_TimeBaseStructure.TIM_RepetitionCounter = 0x0;
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279 TIM_TimeBaseInit(TIM4 ,&TIM_TimeBaseStructure);
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280
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281 /* Channel 1, 2, 3 and 4 Configuration in PWM mode */
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282 TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
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283 TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
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284 TIM_OCInitStructure.TIM_Pulse = 0;
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285 TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
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286 TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low;
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287 TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
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288 TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
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289 TIM_OC2Init(TIM4, &TIM_OCInitStructure);
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290
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291 /* Automatic Output enable, Break, dead time and lock configuration*/
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292 TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable;
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293 TIM_BDTRInitStructure.TIM_OSSIState = TIM_OSSIState_Enable;
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294 TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_1;
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295 TIM_BDTRInitStructure.TIM_DeadTime = 0x75;
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296 TIM_BDTRInitStructure.TIM_Break = TIM_Break_Enable;
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297 TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_High;
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298 TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Enable;
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299
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300 TIM_BDTRConfig(TIM4, &TIM_BDTRInitStructure);
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301
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302 /* TIM1 counter enable */
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303 TIM_Cmd(TIM4,ENABLE);
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304 #else
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305 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13;
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306 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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307 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
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308 GPIO_Init(GPIOD, &GPIO_InitStructure);
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309
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310 GPIO_SetBits(GPIOD, GPIO_Pin_13);
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311 #endif
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312
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313 /* Configure reset pin (PE1) as GPIO out PP */
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314 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;
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315 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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316 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
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317 GPIO_Init(GPIOE, &GPIO_InitStructure);
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318
3
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319 /* Configures the Parallel interface (FSMC) for LCD (Parallel mode) */
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320 /* FSMC_Bank1_NORSRAM4 timing configuration */
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321 p.FSMC_AddressSetupTime = 1;
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322 p.FSMC_AddressHoldTime = 0;
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323 p.FSMC_DataSetupTime = 2;
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324 p.FSMC_BusTurnAroundDuration = 0;
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325 p.FSMC_CLKDivision = 0;
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326 p.FSMC_DataLatency = 0;
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327 p.FSMC_AccessMode = FSMC_AccessMode_A;
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328
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329 /* FSMC_Bank1_NORSRAM4 configured as follows:
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330 - Data/Address MUX = Disable
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331 - Memory Type = SRAM
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332 - Data Width = 16bit
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333 - Write Operation = Enable
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334 - Extended Mode = Disable
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335 - Asynchronous Wait = Disable */
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336 FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM4;
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337 FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
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338 FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
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339 FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
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340 FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
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341 FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
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342 FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
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343 FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
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344 FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
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345 FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
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346 FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
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347 FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
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348 FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
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349 FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
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350 FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
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351
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352 FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
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353
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354 /* Enable FSMC_Bank1_NORSRAM4 */
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355 FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE);
4
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356
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357 /* Initialise LCD panel */
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358
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359 /* Pull reset pin low */
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360 GPIO_ResetBits(GPIOE, GPIO_Pin_1);
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361 Delay(0xafff);
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362 GPIO_SetBits(GPIOE, GPIO_Pin_1);
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363 Delay(0xafff);
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364
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365 id = LCD_RD_Reg(0x00);
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366 if (id != 0x9325) {
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367 printf("LCD ID doesn't match, expected 0x9325 got 0x%x\r\n", id);
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368 return;
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369 }
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370
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371 LCD_WR_Reg(0x00e3, 0x3008); /* Set internal timing */
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372 LCD_WR_Reg(0x00e7, 0x0012); /* Set internal timing */
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373 LCD_WR_Reg(0x00ef, 0x1231); /* Set internal timing */
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374 LCD_WR_Reg(0x0000, 0x0001); /* Start Oscillation */
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375 LCD_WR_Reg(0x0001, 0x0100); /* set SS and SM bit */
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376 LCD_WR_Reg(0x0002, 0x0700); /* set 1 line inversion */
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diff changeset
377
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378 LCD_WR_Reg(0x0003, 0x1030); /* set GRAM write direction and BGR = 0, 262K colours, 1 transfers/pixel. */
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379 LCD_WR_Reg(0x0004, 0x0000); /* Resize register */
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380 LCD_WR_Reg(0x0008, 0x0202); /* set the back porch and front porch */
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381 LCD_WR_Reg(0x0009, 0x0000); /* set non-display area refresh cycle ISC[3:0] */
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382 LCD_WR_Reg(0x000a, 0x0000); /* FMARK function */
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383 LCD_WR_Reg(0x000c, 0x0000); /* RGB interface setting */
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384 LCD_WR_Reg(0x000d, 0x0000); /* Frame marker Position */
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385 LCD_WR_Reg(0x000f, 0x0000); /* RGB interface polarity */
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386
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387 /* Power On sequence */
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388 LCD_WR_Reg(0x0010, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
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389 LCD_WR_Reg(0x0011, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */
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390 LCD_WR_Reg(0x0012, 0x0000); /* VREG1OUT voltage */
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391 LCD_WR_Reg(0x0013, 0x0000); /* VDV[4:0] for VCOM amplitude */
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392 Delay(200); /* Dis-charge capacitor power voltage */
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diff changeset
393 LCD_WR_Reg(0x0010, 0x1690); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
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394 LCD_WR_Reg(0x0011, 0x0227); /* R11h = 0x0221 at VCI = 3.3V, DC1[2:0], DC0[2:0], VC[2:0] */
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395 Delay(50); /* Delay 50ms */
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diff changeset
396 LCD_WR_Reg(0x0012, 0x001c); /* External reference voltage= Vci; */
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397 Delay(50); /* Delay 50ms */
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398 LCD_WR_Reg(0x0013, 0x1800); /* R13 = 1200 when R12 = 009D; VDV[4:0] for VCOM amplitude */
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399 LCD_WR_Reg(0x0029, 0x001c); /* R29 = 000C when R12 = 009D; VCM[5:0] for VCOMH */
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400 LCD_WR_Reg(0x002b, 0x000d); /* Frame Rate = 91Hz */
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diff changeset
401 Delay(50); /* Delay 50ms */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
402 LCD_WR_Reg(0x0020, 0x0000); /* GRAM horizontal Address */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
403 LCD_WR_Reg(0x0021, 0x0000); /* GRAM Vertical Address */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
404
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
405 /* Adjust the Gamma Curve */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
406 LCD_WR_Reg(0x0030, 0x0007);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
407 LCD_WR_Reg(0x0031, 0x0302);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
408 LCD_WR_Reg(0x0032, 0x0105);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
409 LCD_WR_Reg(0x0035, 0x0206);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
410 LCD_WR_Reg(0x0036, 0x0808);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
411 LCD_WR_Reg(0x0037, 0x0206);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
412 LCD_WR_Reg(0x0038, 0x0504);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
413 LCD_WR_Reg(0x0039, 0x0007);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
414 LCD_WR_Reg(0x003c, 0x0105);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
415 LCD_WR_Reg(0x003d, 0x0808);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
416
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
417 /* Set GRAM area */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
418 LCD_WR_Reg(0x0050, 0x0000); /* Horizontal GRAM Start Address */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
419 LCD_WR_Reg(0x0051, 0x00ef); /* Horizontal GRAM End Address */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
420 LCD_WR_Reg(0x0052, 0x0000); /* Vertical GRAM Start Address */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
421 LCD_WR_Reg(0x0053, 0x013f); /* Vertical GRAM Start Address */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
422 LCD_WR_Reg(0x0060, 0xa700); /* Gate Scan Line */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
423 LCD_WR_Reg(0x0061, 0x0001); /* NDL,VLE, REV */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
424 LCD_WR_Reg(0x006a, 0x0000); /* set scrolling line */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
425
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
426 /* Partial Display Control */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
427 LCD_WR_Reg(0x0080, 0x0000);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
428 LCD_WR_Reg(0x0081, 0x0000);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
429 LCD_WR_Reg(0x0082, 0x0000);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
430 LCD_WR_Reg(0x0083, 0x0000);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
431 LCD_WR_Reg(0x0084, 0x0000);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
432 LCD_WR_Reg(0x0085, 0x0000);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
433
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
434 /* Panel Control */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
435 LCD_WR_Reg(0x0090, 0x0010);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
436 LCD_WR_Reg(0x0092, 0x0000);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
437 LCD_WR_Reg(0x0093, 0x0003);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
438 LCD_WR_Reg(0x0095, 0x0110);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
439 LCD_WR_Reg(0x0097, 0x0000);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
440 LCD_WR_Reg(0x0098, 0x0000);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
441 LCD_WR_Reg(0x0007, 0x0133); /* 262K colour and display ON */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
442
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
443 /* Fill panel with white */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
444 LCD_WR_Reg(0x20, 0);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
445 LCD_WR_Reg(0x21, 0x013f);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
446 *(__IO uint16_t *)(Bank1_LCD_C) = 34;
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
447 for (colour1 = 0; colour1 < 76800; colour1++) {
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
448 LCD_WR_Data(0xffff);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
449 }
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
450 colour1 = 0;
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
451
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
452 /* Configure touch screen controller
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
453 *
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
454 * Connected to SPI1 which is shared with the AT45DB161D.
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
455 *
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
456 * The touch screen is selected with PB7.
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
457 * The flash chip is selected with PA4.
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
458 */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
459
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
460 /* Enable SPI1 clock */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
461 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
462
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
463 /* Configure MOSI, MISO and SCLK as alternate function PP */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
464 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
465 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
466 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
467 GPIO_Init(GPIOA, &GPIO_InitStructure);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
468
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
469 /* Configure flash chip select pin (PA4) as GPIO out PP */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
470 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
471 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
472 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
473 GPIO_Init(GPIOA, &GPIO_InitStructure);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
474
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
475 /* Configure touch chip select pin (PB7) as GPIO out PP */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
476 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
477 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
478 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
479 GPIO_Init(GPIOB, &GPIO_InitStructure);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
480
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
481 /* De-select touch & flash */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
482 GPIO_SetBits(GPIOA, GPIO_Pin_4);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
483 GPIO_SetBits(GPIOB, GPIO_Pin_7);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
484
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
485 /* SPI1 Config */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
486 SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
487 SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
488 SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
489 SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
490 SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
491 SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
492 SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64;
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
493 SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
494 SPI_InitStructure.SPI_CRCPolynomial = 7;
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
495 SPI_Init(SPI1, &SPI_InitStructure);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
496
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
497 /* SPI1 enable */
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
498 SPI_Cmd(SPI1, ENABLE);
2c87e30c982d Add LCD init, touch screen writing etc..
Daniel O'Connor <darius@dons.net.au>
parents: 3
diff changeset
499
3
74e9b3baac1e Jumbo commit to make things work.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
500 }