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annotate libs/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/readme.txt @ 85:18b154c447bb

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Add note about 1-wire wiring
author Daniel O'Connor <darius@dons.net.au>
date Thu, 12 Mar 2015 23:22:11 +1030
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1 /**
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2 @page TIM1_DMABURST TIM1 DMA Burst transfer example
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3
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4 @verbatim
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5 ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
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6 * @file TIM/DMABurst/readme.txt
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7 * @author MCD Application Team
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8 * @version V3.5.0
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9 * @date 08-April-2011
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10 * @brief Description of the TIM1 DMA Burst transfer example.
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11 ******************************************************************************
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12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 ******************************************************************************
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19 @endverbatim
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20
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21 @par Example Description
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22
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23 This example shows how to update the TIM1 channel1 period and the duty cycle
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24 using the TIM1 DMA burst feature.
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25
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26 Every update DMA request, the DMA will do 3 transfers of half words into Timer
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27 registers beginning from ARR register.
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28 On the DMA update request, 0x0FFF will be transferred into ARR, 0x0000
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29 will be transferred into RCR, 0x0555 will be transferred into CCR1.
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30
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31 The TIM1CLK frequency is set to SystemCoreClock (Hz), to get TIM1 counter
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32 clock at 24 MHz the Prescaler is computed as following:
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33 - Prescaler = (TIM1CLK / TIM1 counter clock) - 1
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34 SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
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35 and Connectivity line devices and to 24 MHz for Value line devices.
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36
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37 The TIM1 period is 5.8 KHz: TIM1 Frequency = TIM1 counter clock/(ARR + 1)
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38 = 24 MHz / 4096 = 5.8 KHz
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39 The TIM1 CCR1 register value is equal to 0x555, so the TIM1 Channel 1 generates a
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40 PWM signal with a frequency equal to 5.8 KHz and a duty cycle equal to 33.33%:
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41 TIM1 Channel1 duty cycle = (TIM1_CCR1/ TIM1_ARR + 1)* 100 = 33.33%
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42
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43 The PWM waveform can be displayed using an oscilloscope.
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44
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45 @note No need of RCR update, but we should do it because of the ARR and CCR1
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46 mapping.
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47
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48
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49 @par Directory contents
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50
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51 - TIM/DMABurst/stm32f10x_conf.h Library Configuration file
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52 - TIM/DMABurst/stm32f10x_it.c Interrupt handlers
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53 - TIM/DMABurst/stm32f10x_it.h Interrupt handlers header file
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54 - TIM/DMABurst/main.c Main program
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55 - TIM/DMABurst/system_stm32f10x.c STM32F10x system source file
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56
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57 @par Hardware and Software environment
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58
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59 - This example runs on STM32F10x Connectivity line, High-Density, High-Density
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60 Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density
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61 and Low-Density Value line Devices.
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62
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63 - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
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64 Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line),
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65 STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density)
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66 evaluation boards and can be easily tailored to any other supported device
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67 and development board.
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68
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69 - STM32100E-EVAL, STM32100B-EVAL, STM3210C-EVAL, STM3210E-EVAL, STM32100E-EVAL and STM3210B-EVAL Set-up
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70 - Connect the following pins to an oscilloscope to monitor the different
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71 waveforms:
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72 - TIM1 CH1 (PA.08)
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73
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74 @par How to use it ?
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75
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76 In order to make the program work, you must do the following :
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77 - Copy all source files from this example folder to the template folder under
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78 Project\STM32F10x_StdPeriph_Template
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79 - Open your preferred toolchain
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80 - Rebuild all files and load your image into target memory
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81 - Run the example
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82
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83 @note
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84 - Low-density Value line devices are STM32F100xx microcontrollers where the
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85 Flash memory density ranges between 16 and 32 Kbytes.
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86 - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
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87 microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
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88 - Medium-density Value line devices are STM32F100xx microcontrollers where
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89 the Flash memory density ranges between 64 and 128 Kbytes.
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90 - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
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91 microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
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92 - High-density Value line devices are STM32F100xx microcontrollers where
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93 the Flash memory density ranges between 256 and 512 Kbytes.
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94 - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
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95 the Flash memory density ranges between 256 and 512 Kbytes.
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96 - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
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97 the Flash memory density ranges between 512 and 1024 Kbytes.
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98 - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
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99
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100 * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
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101 */