Mercurial > ~darius > hgwebdir.cgi > pa
changeset 21:ba213b2ace45
Add various missing symbols and/or parts.
| author | Daniel O'Connor <darius@dons.net.au> |
|---|---|
| date | Mon, 27 Nov 2023 13:21:20 +1030 |
| parents | 3341ef03cb66 |
| children | 8d7aa773caeb |
| files | LMV7219.asy LMV7219.lib Modulator.asy STP7N60M2x2.asc STP7N60M2x2.asy TP65H150.asy TP65H150.lib |
| diffstat | 7 files changed, 398 insertions(+), 0 deletions(-) [+] |
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/LMV7219.asy Mon Nov 27 13:21:20 2023 +1030 @@ -0,0 +1,34 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LMV7219 +SYMATTR Prefix X +SYMATTR Description Ti LMV7219 comparator +SYMATTR ModelFile LMV7219.lib +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/LMV7219.lib Mon Nov 27 13:21:20 2023 +1030 @@ -0,0 +1,106 @@ +*////////////////////////////////////////////////////////////////////// +* (C) National Semiconductor, Corporation. +* Models developed and under copyright by: +* National Semiconductor, Corporation. +*///////////////////////////////////////////////////////////////////// +* Legal Notice: +* The model may be copied, and distributed without any modifications; +* however, reselling or licensing the material is illegal. +* We reserve the right to make changes to the model without prior notice. +* Pspice Models are provided "AS IS, WITH NO WARRANTY OF ANY KIND" +*//////////////////////////////////////////////////////////////////// +*LMV7219 7nsec 2.7 to 5V Comparator with Rail-to-Rail Output +* PINOUT ORDER +IN -IN VCC VSS OUT +.SUBCKT LMV7219 22 6 1 2 18 +R1 1 3 10.0E6 +V3 49 2 -1.2 +V5 4 6 0.001 +V4 1 42 0.6 +Q1 47 47 42 Q1M +I3 47 2 40.0E-6 +V15 48 2 -1.2 +I2 1 2 2.1E-3 +D1 50 46 D1M +R3 5 46 3.5E6 +R2 1 2 11.4E3 +E6 43 0 30 0 1.0 +E7 28 0 32 0 1.0 +E8 8 0 26 0 1.0 +G1 0 10 46 27 0.01 +R6 10 0 100.0 +R7 10 9 10.0 +C5 9 0 62.0E-12 +G2 0 11 10 0 -22.7E-3 +R8 11 0 14.0E6 +D5 12 11 DN4 +D6 11 12 DN4 +E1 12 0 13 0 1.0 +R9 11 13 74.0 +C6 13 0 0.05E-12 +G3 0 14 13 0 0.01 +R10 14 0 100.0 +M1 18 14 1 1 WPM L=100U W=100U +M2 18 14 2 2 WNM L=100U W=100U +RO1 1 18 200.0E6 +RO2 2 18 100.0E6 +C1 14 0 10.0E-12 +R14 46 24 1.0E9 +R15 5 24 1.0E9 +G6 0 26 24 0 5.6E-4 +D8 34 1 D8M +V9 34 38 0.7 +C2 14 18 1.0E-14 +C3 18 0 1.0E-13 +E2 16 0 14 0 1.0 +RD3 16 0 1.0E18 +E10 15 16 1 2 -0.7 +R4 33 15 750.0 +R16 26 25 1.0 +L1 25 0 3.2E-8 +E3 5 27 39 0 1.0 +I1 0 37 1.0E-3 +G7 0 32 2 0 6.0E-5 +G8 0 30 1 0 6.0E-5 +R24 30 29 1.0 +L2 29 0 1.6E-7 +R25 32 31 1.0 +L3 31 0 1.6E-7 +V13 41 37 -0.71465 +D15 40 36 D8M +V12 13 36 0.7 +E4 39 0 0 33 1.0E6 +R29 33 43 1.0 +R30 33 28 1.0 +R31 33 8 1.0 +R32 39 33 1.0 +E5 38 13 41 0 1.0 +E9 40 2 41 0 1.0 +D10 37 0 D8M +D2 52 5 D1M +Q3 3 47 42 QAM 10 +R19 3 44 1.0E3 +R20 3 45 999.0 +R22 46 48 1.0E3 +R23 5 49 999.0 +Q4 50 4 44 Q4M +Q5 52 22 45 Q5M +RD1 27 0 1.0E18 +RD2 41 0 1.0E18 +.MODEL D8M D IS=1.0E-15 +.MODEL DN4 D BV=100.0 CJO=4.0E-12 IS=7.0E-9 ++ M=0.45 N=2 RS=0.8 TT=6.0E-9 VJ=0.6 +.MODEL D1M D BV=5.33E+1 CJO=2.0E-14 ++ IBV=5.0E-8 IS=4.69E-16 M=0.333 N=1.95 ++ RS=2.18E-1 TT=2.9E-9 VJ=0.75 +.MODEL Q1M PNP BF=200.0 +.MODEL QAM PNP BF=100.0 +.MODEL Q4M PNP BF=200.0 +.MODEL Q5M PNP BF=250.0 +.MODEL WNM NMOS LEVEL=1 KP=0.015 RD=32.0 RS=1.0 ++ VTO=1.0 IS=1.0E-14 FC=0.5 MJ=0.5 MJSW=0.5 PB=0.8 ++ PHI=0.6 TOX=1.0E-7 UO=600.0 TPG=1 AF=1 +.MODEL WPM PMOS LEVEL=1 KP=0.015 RD=32.0 RS=1.0 ++ VTO=-1.0 IS=1.0E-14 FC=0.5 MJ=0.5 MJSW=0.5 PB=0.8 ++ PHI=0.6 TOX=1.0E-7 UO=600.0 TPG=1 AF=1 +.ENDS + \ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/Modulator.asy Mon Nov 27 13:21:20 2023 +1030 @@ -0,0 +1,16 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal -48 -72 64 72 +WINDOW 0 8 -72 Bottom 2 +PIN 64 -48 RIGHT 8 +PINATTR PinName DRIVE +PINATTR SpiceOrder 1 +PIN 64 -16 RIGHT 8 +PINATTR PinName GATE +PINATTR SpiceOrder 2 +PIN 64 16 RIGHT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 3 +PIN 64 48 RIGHT 8 +PINATTR PinName SHAPE +PINATTR SpiceOrder 4
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/STP7N60M2x2.asy Mon Nov 27 13:21:20 2023 +1030 @@ -0,0 +1,13 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal -96 -56 96 56 +WINDOW 0 0 -56 Bottom 2 +PIN -96 0 LEFT 8 +PINATTR PinName MOD_RAIL +PINATTR SpiceOrder 1 +PIN -96 32 LEFT 8 +PINATTR PinName RFDrive +PINATTR SpiceOrder 2 +PIN 96 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TP65H150.asy Mon Nov 27 13:21:20 2023 +1030 @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -80 0 -24 0 +LINE Normal -24 -24 -24 -38 +LINE Normal -24 8 -24 -8 +LINE Normal -24 38 -24 24 +LINE Normal 16 32 16 80 +LINE Normal -24 32 16 32 +LINE Normal -24 32 -24 32 +LINE Normal 16 -32 -24 -32 +LINE Normal 16 -80 16 -32 +LINE Normal -11 25 6 32 +LINE Normal -11 39 -11 25 +LINE Normal 6 32 -11 39 +CIRCLE Normal 48 48 -48 -48 +WINDOW 0 32 -48 Left 1 +WINDOW 3 32 48 Left 1 +SYMATTR Value TP65H150 +SYMATTR Prefix x +SYMATTR ModelFile TP65H150.lib +PIN -80 0 NONE 8 +PINATTR PinName Gate +PINATTR SpiceOrder 2 +PIN 16 -80 NONE 8 +PINATTR PinName Drain +PINATTR SpiceOrder 1 +PIN 16 80 NONE 8 +PINATTR PinName Source +PINATTR SpiceOrder 3
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TP65H150.lib Mon Nov 27 13:21:20 2023 +1030 @@ -0,0 +1,200 @@ +.subckt TP65H150 301 302 303 +* GROUP A: 301=D1, 302=G1, 303=S1 +* +* NODE 000 - 099: RESERVED FOR CAP EMULATION +* NODE 100 - 199: HEMT_A AND NMOS_A +* NODE 300 - 399: PIN AND CONNECTION +* +* Part A: 101=drain A, 152=gate A, 199=source A +* HEMT_A: 101=drainHA, 102=gateHA, 103=sourceHA +* NMOS_A: 151=drainMA, 152=gateMA, 153=sourceMA +* +* ver 0.1, JAN 17, 2019, By Feng Qi @ Transphorm +* ver 0.2, MAY 14, 2019, By Feng Qi @ Transphorm +* Correct value of Rdson + +************************ +************************ +*** Part A Begin *** +************************ +* 101=drain A, 152=gate A, 199=source A + +************************** +** Connection A Begin ** + +Li1A 103 151 0.26nH +Li2A 102 198 0.20nH +Ri2A 198 199 0.12 +Li3A 153 197 0.33nH +Ri3A 197 199 0.01 + +** Connection A End ** +************************ + + +******************* +** HEMT_A Begin ** +* xxxx +* 101=drainHA, 102=gateHA, 103=sourceHA + + +** HEMT_A Body ** + +J1A 104 102 103 MJ1A 1.2 +.model MJ1A NJF vto -22 beta 0.25 lambda 0.005 rs 0.01 ++ cgs 30PF cgd 3.5PF is=1f m=0.3 + +J2A 105 102 104 MJ2A 1.2 +.model MJ2A NJF vto -75 beta 0.25 lambda 0.005 ++ cgs 20PF cgd 35PF is=1f m=0.35 + +J3A 101 102 105 MJ3A 1.2 +.model MJ3A NJF vto -210 beta 0.25 lambda 0.005 rd 0.01 ++ cgs 10PF cgd 350PF is=1f m=0.4 + + +** HEMT_A Leakage Compensation ** + +DL1A 106 101 MDLA 1.2 +DL2A 106 103 MDLA 1.2 +.model MDLA D is=0.05uA cjo=0 + + +** HEMT_A Cap Compensation ** + +CJA 101 103 10pF + + +** HEMT_A End ** +****************** + + +******************** +** NMOS_A Begin ** +* xxxx +* 151=drainMA, 152=gateMA, 153=sourceMA + +MA 159 157 158 158 MMA L=100u W=100u +.MODEL MMA NMOS LEVEL=1 IS=1e-32 ++VTO=3.9 LAMBDA=0 KP=15 ++CGSO=7.5e-06 CGDO=1e-11 + + +DM1A 153 151 MDMA +.MODEL MDMA D IS=2.44e-12 RS=0.0035 N=1.07 BV=33 ++IBV=0.00025 EG=1 XTI=1 TT=3.0e-09 ++CJO=6.5e-10 VJ=1.47 M=0.52 FC=0.5 + +RMA 153 151 1e+07 +RMDA 159 151 0.0001 +RMGA 152 157 2.2e-3 +RMSA 158 153 0.0011 + + +RMLA 155 160 1 +FM2A 157 159 VM2A -1 +VM2A 154 0 0 +EMA 160 0 159 157 1 +CMA 161 160 4.0e-10 +FM1A 157 159 VM1A -1 +VM1A 161 156 0 +RMCA 156 160 1 + +DM2A 154 155 MDM1A +.MODEL MDM1A D IS=1e-32 N=50 ++CJO=0.75e-10 VJ=4.0 M=0.3 FC=1e-08 + +DM3A 0 155 MDM2A +.MODEL MDM2A D IS=1e-10 N=0.41 RS=3e-06 + +DM4A 0 156 MDM3A +.MODEL MDM3A D IS=1e-10 N=0.41 + +** NMOS_A End ** +****************** + + +** PartA Cap Compensation ** + +CGDA 321 101 4pF + +********************* +*** PartA End *** +********************* +********************* + + + +******************************** +******************************** +*** Pin Connection Begin *** +******************************** + + +******************** +** 301=D1 Begin ** +* from 101=drainA to 301=D1 +* +*L315 301 311 1.68n +*R315 301 311 40 +*R311 311 101 54m +*L311 311 312 0.0129n +*R312 312 101 27m +*L312 312 313 0.04322n +*R313 313 101 13.5m +*L314 313 314 0.1448n +*R314 314 101 6.75m +* +** 301=D1 End ** +****************** +R311 101 311 0.2m +L311 311 301 0.01n +R312 101 301 0.2m + +******************** +** 302=G1 Begin ** +* from 152=GateA to 302=G1 +* +*L325 302 321 2.86n +*R325 302 321 40 +*R321 321 152 1145m +*L321 321 322 0.053n +*R322 322 152 408.93m +*L322 322 323 0.06784n +*R323 323 152 146m +*L324 323 324 0.08684n +*R324 324 152 52.16m +* +** 302=G1 End ** +****************** +R321 152 321 0.2m +L321 321 302 0.01n +R322 152 302 0.2m + +******************** +** 303=S1 Begin ** +* from 199=sourceA to 303=S1 +* +*L335 303 331 0.65n +*R335 303 331 2 +*R331 331 199 40.5m +*L331 331 332 0.0097n +*R332 332 199 20.25m +*L332 332 333 0.0398n +*R333 333 199 10.125m +*L334 333 334 0.163n +*R334 334 199 5.0625m +* +** 303=S1 End ** +****************** +R331 199 331 0.2m +L331 331 303 0.01n +R332 331 303 0.2m + +****************************** +*** Pin Connection End *** +****************************** +****************************** + + +.ends TP65H150 \ No newline at end of file