;
; Copyright (c) 2025 Daniel O'Connor
;

.program ctrl
.define TRIGGER_IRQ 0

PUBLIC init:
; Assert all 0s
    mov pins, null
    nop
; Wait for start trigger and clear IRQ
    wait 1 irq TRIGGER_IRQ
.wrap_target
    out pins 8 [1]
    nop        [1]
.wrap

% c-sdk {
static inline void ctrl_program_init(PIO pio, uint sm, uint offset, uint pin, uint clkdiv) {
    pio_sm_config c = ctrl_program_get_default_config(offset);

    // Set the OUT base pin to the provided `pin` parameter.
    // Note: We only need 6 pins but pull a byte at a time to make
    // generating the data simpler
    sm_config_set_out_pins(&c, pin, 6);
    // Set the pin directions to output at the PIO
    pio_sm_set_consecutive_pindirs(pio, sm, pin, 6, true);
    // Connect these GPIOs to this PIO block
    for (int i = 0; i < 6; i++)
        pio_gpio_init(pio, pin + i);

    sm_config_set_out_shift(
        &c,
        true,  // Shift-to-right
        true,  // Autopull enabled
        8      // Autopull threshold (bits!)
    );

    // We only send, so disable the RX FIFO to make the TX FIFO deeper.
    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);

    sm_config_set_clkdiv(&c, clkdiv);

    // Load our configuration (but don't start)
    pio_sm_init(pio, sm, offset, &c);
}

static inline uint ctrl_reset_instr (uint offset) {
    // encode a "jmp init side 0" instruction for the state machine
    return pio_encode_jmp (offset + ctrl_offset_init);
}
%}