Mercurial > ~darius > hgwebdir.cgi > modulator
comparison modulator.c @ 27:e1d8fe3e418a
Run PIOs at 1x with delays and sync.
Can now use a single trigger to set both DAC & ctrl.
DAC [still] jitters against the ctrl though..
author | Daniel O'Connor <darius@dons.net.au> |
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date | Wed, 26 Feb 2025 11:03:59 +1030 |
parents | 336f06fa6e47 |
children | 600a394629e6 |
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26:336f06fa6e47 | 27:e1d8fe3e418a |
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360 printf("Unable to load DAC program\n"); | 360 printf("Unable to load DAC program\n"); |
361 __breakpoint(); | 361 __breakpoint(); |
362 } | 362 } |
363 dac_sm = pio_claim_unused_sm(pulse_pio, true); | 363 dac_sm = pio_claim_unused_sm(pulse_pio, true); |
364 // Data is GPIO7 to GPIO14, clock is GPIO15 | 364 // Data is GPIO7 to GPIO14, clock is GPIO15 |
365 // Clock divisor of 2 so it runs at 60MHz and | 365 // Clock divisor of 1 but the PIO has delays so it runs at 60MHz |
366 // generates a 30MHz clock | 366 // and generates a 30MHz clock |
367 dac_program_init(pulse_pio, dac_sm, dac_pio_sm_offset, DACOUT_GPIO, 2); | 367 dac_program_init(pulse_pio, dac_sm, dac_pio_sm_offset, DACOUT_GPIO, 1); |
368 | 368 |
369 // Configure a channel to write 32 bits at a time to PIO0 | 369 // Configure a channel to write 32 bits at a time to PIO0 |
370 // SM0's TX FIFO, paced by the data request signal from that peripheral. | 370 // SM0's TX FIFO, paced by the data request signal from that peripheral. |
371 dac_dma_chan = dma_claim_unused_channel(true); | 371 dac_dma_chan = dma_claim_unused_channel(true); |
372 dma_channel_config dac_dmac = dma_channel_get_default_config(dac_dma_chan); | 372 dma_channel_config dac_dmac = dma_channel_get_default_config(dac_dma_chan); |
396 if (ctrl_pio_sm_offset < 0) { | 396 if (ctrl_pio_sm_offset < 0) { |
397 printf("Unable to load ctrl program\n"); | 397 printf("Unable to load ctrl program\n"); |
398 __breakpoint(); | 398 __breakpoint(); |
399 } | 399 } |
400 ctrl_sm = pio_claim_unused_sm(pulse_pio, true); | 400 ctrl_sm = pio_claim_unused_sm(pulse_pio, true); |
401 ctrl_program_init(pulse_pio, ctrl_sm, ctrl_pio_sm_offset, CTRLOUT_GPIO, 2); | 401 ctrl_program_init(pulse_pio, ctrl_sm, ctrl_pio_sm_offset, CTRLOUT_GPIO, 1); |
402 | 402 |
403 // Configure a channel to write 32 bits at a time to PIO0 | 403 // Configure a channel to write 32 bits at a time to PIO0 |
404 // SM0's TX FIFO, paced by the data request signal from that peripheral. | 404 // SM0's TX FIFO, paced by the data request signal from that peripheral. |
405 ctrl_dma_chan = dma_claim_unused_channel(true); | 405 ctrl_dma_chan = dma_claim_unused_channel(true); |
406 dma_channel_config ctrl_dmac = dma_channel_get_default_config(ctrl_dma_chan); | 406 dma_channel_config ctrl_dmac = dma_channel_get_default_config(ctrl_dma_chan); |
425 if (trigger_pio_sm_offset < 0) { | 425 if (trigger_pio_sm_offset < 0) { |
426 printf("Unable to load trigger program\n"); | 426 printf("Unable to load trigger program\n"); |
427 __breakpoint(); | 427 __breakpoint(); |
428 } | 428 } |
429 uint trigger_sm = pio_claim_unused_sm(pulse_pio, true); | 429 uint trigger_sm = pio_claim_unused_sm(pulse_pio, true); |
430 trigger_program_init(pulse_pio, trigger_sm, trigger_pio_sm_offset, TRIGIN_GPIO, 2); | 430 trigger_program_init(pulse_pio, trigger_sm, trigger_pio_sm_offset, TRIGIN_GPIO, 1); |
431 #endif | 431 #endif |
432 | 432 |
433 // Start & sync all state machines | |
434 // This is necessary to avoid any jitter and to make the | |
435 // trigger sync work correctly | |
436 pio_enable_sm_mask_in_sync(pulse_pio, | |
437 1u << dac_sm | | |
438 1u << ctrl_sm | | |
439 #ifdef WITH_TRIGGER | |
440 1u << trigger_sm | |
441 #endif | |
442 ); | |
433 // | 443 // |
434 // Setup PWM | 444 // Setup PWM |
435 // Used here to output a trigger which gets fed back into the trigger SM | 445 // Used here to output a trigger which gets fed back into the trigger SM |
436 // | 446 // |
437 // 120MHz / 250 = 480kHz base | 447 // 120MHz / 250 = 480kHz base |
438 // Maximum divisor is only 256 which limits the low end, | 448 // Maximum divisor is only 256 which limits the low end, |
439 // could further subdivide in the IRQ handler | 449 // could further subdivide in the IRQ handler |
440 pwm_config c = pwm_get_default_config(); | 450 pwm_config c = pwm_get_default_config(); |
441 pwm_config_set_clkdiv_int(&c, 250); | 451 pwm_config_set_clkdiv_int(&c, 250); |
442 // 8Hz | 452 // 80Hz |
443 pwm_config_set_wrap(&c, 60000 - 1); | 453 pwm_config_set_wrap(&c, 6000 - 1); |
444 | 454 |
445 gpio_set_function(TRIGOUT_GPIO, GPIO_FUNC_PWM); | 455 gpio_set_function(TRIGOUT_GPIO, GPIO_FUNC_PWM); |
446 | 456 |
447 slice_num = pwm_gpio_to_slice_num(TRIGOUT_GPIO); | 457 slice_num = pwm_gpio_to_slice_num(TRIGOUT_GPIO); |
448 pwm_init(slice_num, &c, true); | 458 pwm_init(slice_num, &c, true); |