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comparison modulator.c @ 17:a249e4727b01

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Move SM reset & DMA reprogramming to DMA IRQ handler, only trigger in PWM IRQ handler. Otherwise we would collide with the setup in the main loop.
author Daniel O'Connor <darius@dons.net.au>
date Tue, 25 Feb 2025 13:40:57 +1030
parents 56a79dce90e9
children f1e44afb41a3
comparison
equal deleted inserted replaced
16:56a79dce90e9 17:a249e4727b01
100 void 100 void
101 dma_handler(void) { 101 dma_handler(void) {
102 // Clear the interrupt request. 102 // Clear the interrupt request.
103 dma_hw->ints0 = 1u << dac_dma_chan; 103 dma_hw->ints0 = 1u << dac_dma_chan;
104 104
105 // Disabled for now, manual trigger only 105 printf("DAC: transfers %lu\n", dma_channel_hw_addr(dac_dma_chan)->transfer_count);
106 #if 0 106 printf("DAC: transfers %lu\n", dma_channel_hw_addr(ctrl_dma_chan)->transfer_count);
107
107 // Reset DAQ & ctrl PIO SMs so they are waiting for a trigger 108 // Reset DAQ & ctrl PIO SMs so they are waiting for a trigger
108 pio_sm_exec(pulse_pio, dac_sm, pio_encode_jmp(dac_pio_sm_offset)); 109 pio_sm_exec(pulse_pio, dac_sm, pio_encode_jmp(dac_pio_sm_offset));
109 pio_sm_exec(pulse_pio, ctrl_sm, pio_encode_jmp(ctrl_pio_sm_offset)); 110 pio_sm_exec(pulse_pio, ctrl_sm, pio_encode_jmp(ctrl_pio_sm_offset));
110
111 // Setup next pulse data & ctrl DMA addresses
112 dma_channel_set_read_addr(dac_dma_chan, pulse_data, true);
113 dma_channel_set_read_addr(ctrl_dma_chan, pulse_ctrl, true);
114 #endif
115 }
116
117
118 void
119 pwm_wrap(void) {
120 pwm_clear_irq(slice_num);
121
122 // Reset DAQ & ctrl PIO SMs so they are waiting for a trigger
123 pio_sm_exec(pulse_pio, dac_sm, pio_encode_jmp(dac_pio_sm_offset));
124 pio_sm_exec(pulse_pio, ctrl_sm, pio_encode_jmp(ctrl_pio_sm_offset));
125
126 printf("DAC: transfers %lu\n", dma_channel_hw_addr(dac_dma_chan)->transfer_count);
127 printf("DAC: transfers %lu\n", dma_channel_hw_addr(ctrl_dma_chan)->transfer_count);
128 111
129 // Setup next pulse data & ctrl DMA addresses 112 // Setup next pulse data & ctrl DMA addresses
130 dma_channel_wait_for_finish_blocking(dac_dma_chan); 113 dma_channel_wait_for_finish_blocking(dac_dma_chan);
131 dma_channel_set_read_addr(dac_dma_chan, pulse_data, true); 114 dma_channel_set_read_addr(dac_dma_chan, pulse_data, true);
132 dma_channel_wait_for_finish_blocking(ctrl_dma_chan); 115 dma_channel_wait_for_finish_blocking(ctrl_dma_chan);
133 dma_channel_set_read_addr(ctrl_dma_chan, pulse_ctrl, true); 116 dma_channel_set_read_addr(ctrl_dma_chan, pulse_ctrl, true);
117 }
118
119
120 void
121 pwm_wrap(void) {
122 pwm_clear_irq(slice_num);
134 123
135 // Manually trigger DAQ SM (cleared by SM) 124 // Manually trigger DAQ SM (cleared by SM)
136 pio0->irq_force = 1 << 0; 125 pio0->irq_force = 1 << 0;
137 126
138 // 'scope trigger 127 // 'scope trigger