comparison modulator.c @ 10:98880b18bcc1

Reset DAC PIO and use force trigger to do manual trigger.
author Daniel O'Connor <darius@dons.net.au>
date Mon, 24 Feb 2025 12:12:09 +1030
parents 3acdebd7eec7
children e9d12b36cfcc
comparison
equal deleted inserted replaced
9:3acdebd7eec7 10:98880b18bcc1
49 #define SENSE 0x01 49 #define SENSE 0x01
50 #define GATE 0x02 50 #define GATE 0x02
51 #define PHINV 0x04 51 #define PHINV 0x04
52 #define PACTIVE 0x08 52 #define PACTIVE 0x08
53 53
54 // DMA channel to feed DAC PIO
54 static int dma_chan; 55 static int dma_chan;
56 // Pulse shape data
55 uint8_t pulse_data[65536]; 57 uint8_t pulse_data[65536];
58 // Pulse control data
56 uint8_t pulse_ctrl[65536]; 59 uint8_t pulse_ctrl[65536];
60 // PWM slice for PRF timer
57 unsigned slice_num = 0; 61 unsigned slice_num = 0;
58 PIO pulse_pio; 62 // DAC PIO
63 PIO pulse_pio = pio0;
64 // DAC SM
59 uint pulse_sm; 65 uint pulse_sm;
60 66 // Instruction offset for DAC PIO program
67 uint pulse_pio_sm_offset;
61 /* 68 /*
62 * Use a DMA channel to feed PIO0 SM0 with pulse data. 69 * Use a DMA channel to feed PIO0 SM0 with pulse data.
63 * Each DMA transfer is a single pulse. 70 * Each DMA transfer is a single pulse.
64 * 71 *
65 * The PIO state machine waits to be triggered before starting 72 * The PIO state machine waits to be triggered before starting
71 */ 78 */
72 void 79 void
73 dma_handler(void) { 80 dma_handler(void) {
74 // Clear the interrupt request. 81 // Clear the interrupt request.
75 dma_hw->ints0 = 1u << dma_chan; 82 dma_hw->ints0 = 1u << dma_chan;
76 // Give the channel a new wave table entry to read from, and re-trigger it
77 //dma_channel_set_read_addr(dma_chan, shaped_trap_dat_start, true);
78 // Reset pulse state machine back to waiting for trigger
79 //pio_sm_exec(pulse_pio, pulse_sm, pio_encode_jump(0);
80 } 83 }
81 84
82 85
83 void 86 void
84 pwm_wrap(void) { 87 pwm_wrap(void) {
88 91
89 gpio_put(PICO_DEFAULT_LED_PIN, state); 92 gpio_put(PICO_DEFAULT_LED_PIN, state);
90 state = !state; 93 state = !state;
91 #endif 94 #endif
92 95
93 // Trigger another pulse read out 96 // Reset DAQ PIO SM so it is waiting for a trigger
97 pio_sm_exec(pulse_pio, pulse_sm, pio_encode_jmp(pulse_pio_sm_offset));
98
99 // Setup next pulse DMA address
94 dma_channel_set_read_addr(dma_chan, pulse_data, true); 100 dma_channel_set_read_addr(dma_chan, pulse_data, true);
101
102 // Manually trigger DAQ SM (cleared by SM)
103 pio0->irq_force = 1 << 0;
104
95 gpio_put(2, 1); 105 gpio_put(2, 1);
96 gpio_put(2, 0); 106 gpio_put(2, 0);
97 } 107 }
98 108
99 // Calculate pulse shape data 109 // Calculate pulse shape data
302 } 312 }
303 now = get_absolute_time(); 313 now = get_absolute_time();
304 unsigned long long diff = absolute_time_diff_us(then, now); 314 unsigned long long diff = absolute_time_diff_us(then, now);
305 printf("Pulse computation took %lld usec and created %lu samples - %.1f nsec/sample\n", 315 printf("Pulse computation took %lld usec and created %lu samples - %.1f nsec/sample\n",
306 diff, idx, (float)diff * 1000.0 / idx); 316 diff, idx, (float)diff * 1000.0 / idx);
307 __breakpoint(); 317 //__breakpoint();
308 318
309 // Load the clocked_input program, and configure a free state machine 319 // Load the clocked_input program, and configure a free state machine
310 // to run the program. 320 // to run the program.
311 PIO pulse_pio = pio0; 321 pulse_pio_sm_offset = pio_add_program(pulse_pio, &dac_program);
312 uint offset = pio_add_program(pulse_pio, &dac_program);
313 uint pulse_sm = pio_claim_unused_sm(pulse_pio, true); 322 uint pulse_sm = pio_claim_unused_sm(pulse_pio, true);
314 // Data is GPIO7 to GPIO14, clock is GPIO15 323 // Data is GPIO7 to GPIO14, clock is GPIO15
315 // Clock divisor of 2 so it runs at 60MHz and 324 // Clock divisor of 2 so it runs at 60MHz and
316 // generates a 30MHz clock 325 // generates a 30MHz clock
317 dac_program_init(pulse_pio, pulse_sm, offset, 7, 2); 326 dac_program_init(pulse_pio, pulse_sm, pulse_pio_sm_offset, 7, 2);
318 327
319 // Configure a channel to write 32 bits at a time to PIO0 328 // Configure a channel to write 32 bits at a time to PIO0
320 // SM0's TX FIFO, paced by the data request signal from that peripheral. 329 // SM0's TX FIFO, paced by the data request signal from that peripheral.
321 dma_chan = dma_claim_unused_channel(true); 330 dma_chan = dma_claim_unused_channel(true);
322 dma_channel_config dmac = dma_channel_get_default_config(dma_chan); 331 dma_channel_config dmac = dma_channel_get_default_config(dma_chan);