Mercurial > ~darius > hgwebdir.cgi > modulator
comparison dac.pio @ 28:600a394629e6
Use 8 bit auto pull otherwise the PIOs jitter (due to DMA contention I guess?)
Don't need to unroll the PIO loops.
Create PIo function to reset each PIO.
Check the DMA IRQ is for us - we get unknown IRQs which need to be ignored or things break.
author | Daniel O'Connor <darius@dons.net.au> |
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date | Thu, 27 Feb 2025 13:58:37 +1030 |
parents | e1d8fe3e418a |
children |
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27:e1d8fe3e418a | 28:600a394629e6 |
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5 .program dac | 5 .program dac |
6 .define TRIGGER_IRQ 0 | 6 .define TRIGGER_IRQ 0 |
7 ; Need 1 side set pin, the clock | 7 ; Need 1 side set pin, the clock |
8 .side_set 1 | 8 .side_set 1 |
9 | 9 |
10 PUBLIC init: | |
10 ; Clock in a 0 byte | 11 ; Clock in a 0 byte |
11 mov pins, null side 0 | 12 mov pins, null side 0 |
12 nop side 1 | 13 nop side 1 |
13 ; Wait for start trigger and clear IRQ | 14 ; Wait for start trigger and clear IRQ |
14 wait 1 irq TRIGGER_IRQ side 0 | 15 wait 1 irq TRIGGER_IRQ side 0 |
15 ; Clock DAC and write data from the FIFO | 16 ; Clock DAC and write data from the FIFO |
16 ; DAC clocks data in on the rising clock edge | 17 ; DAC clocks data in on the rising clock edge |
17 .wrap_target | 18 .wrap_target |
18 out pins 8 side 0 [1] | |
19 nop side 1 [1] | |
20 out pins 8 side 0 [1] | |
21 nop side 1 [1] | |
22 out pins 8 side 0 [1] | |
23 nop side 1 [1] | |
24 out pins 8 side 0 [1] | 19 out pins 8 side 0 [1] |
25 nop side 1 [1] | 20 nop side 1 [1] |
26 .wrap | 21 .wrap |
27 | 22 |
28 % c-sdk { | 23 % c-sdk { |
36 pio_sm_set_consecutive_pindirs(pio, sm, pin, 9, true); | 31 pio_sm_set_consecutive_pindirs(pio, sm, pin, 9, true); |
37 // Connect these GPIOs to this PIO block | 32 // Connect these GPIOs to this PIO block |
38 for (int i = 0; i < 9; i++) | 33 for (int i = 0; i < 9; i++) |
39 pio_gpio_init(pio, pin + i); | 34 pio_gpio_init(pio, pin + i); |
40 | 35 |
36 // Configure sideset pin to use for clock | |
37 sm_config_set_sideset_pins(&c, pin + 8); | |
38 | |
41 sm_config_set_out_shift( | 39 sm_config_set_out_shift( |
42 &c, | 40 &c, |
43 true, // Shift-to-right | 41 true, // Shift-to-right |
44 true, // Autopull enabled | 42 true, // Autopull enabled |
45 32 // Autopull threshold (bits!) | 43 8 // Autopull threshold (bits!) |
46 ); | 44 ); |
47 | |
48 // Configure sideset pin to use for clock | |
49 sm_config_set_sideset_pins(&c, pin + 8); | |
50 | 45 |
51 // We only send, so disable the RX FIFO to make the TX FIFO deeper. | 46 // We only send, so disable the RX FIFO to make the TX FIFO deeper. |
52 sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX); | 47 sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX); |
53 | 48 |
54 sm_config_set_clkdiv(&c, clkdiv); | 49 sm_config_set_clkdiv(&c, clkdiv); |
55 | 50 |
56 // Load our configuration | 51 // Load our configuration (but don't start) |
57 pio_sm_init(pio, sm, offset, &c); | 52 pio_sm_init(pio, sm, offset, &c); |
58 } | 53 } |
54 | |
55 static inline uint dac_reset_instr (uint offset) { | |
56 // encode a "jmp init side 0" instruction for the state machine | |
57 return pio_encode_jmp (offset + dac_offset_init) | pio_encode_sideset (1, 0); | |
58 } | |
59 %} | 59 %} |