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comparison fifo.xco @ 1:f88da01700da GSOFT-MEMEC-1-REL

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Initial import of test project for Memec 3SxLC board with Xilinx XC3S400. Uses a FIFO and flashes some LEDs.
author darius
date Fri, 24 Feb 2006 14:01:25 +0000
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0:7390b436dd20 1:f88da01700da
1 # BEGIN Project Options
2 SET flowvendor = Foundation_iSE
3 SET vhdlsim = True
4 SET verilogsim = True
5 SET workingdirectory = C:\Temp\Memec-test
6 SET speedgrade = -5
7 SET simulationfiles = Behavioral
8 SET asysymbol = True
9 SET addpads = False
10 SET device = xc3s400
11 SET implementationfiletype = Edif
12 SET busformat = BusFormatAngleBracketNotRipped
13 SET foundationsym = False
14 SET package = pq208
15 SET createndf = False
16 SET designentry = VHDL
17 SET devicefamily = spartan3
18 SET formalverification = False
19 SET removerpms = False
20 # END Project Options
21 # BEGIN Select
22 SELECT Asynchronous_FIFO family Xilinx,_Inc. 6.1
23 # END Select
24 # BEGIN Parameters
25 CSET create_rpm=false
26 CSET read_acknowledge=false
27 CSET almost_empty_flag=false
28 CSET write_acknowledge=false
29 CSET memory_type=block
30 CSET read_acknowledge_sense=active_high
31 CSET read_count_width=2
32 CSET fifo_depth=15
33 CSET component_name=fifo
34 CSET write_count_width=2
35 CSET write_count=false
36 CSET read_count=false
37 CSET write_error=false
38 CSET read_error=false
39 CSET read_error_sense=active_high
40 CSET almost_full_flag=false
41 CSET write_acknowledge_sense=active_high
42 CSET write_error_sense=active_high
43 CSET input_data_width=4
44 # END Parameters
45 GENERATE
46