Mercurial > ~darius > hgwebdir.cgi > memec-test

diff fifo.xco @ 1:f88da01700da GSOFT-MEMEC-1-REL
Initial import of test project for Memec 3SxLC board with Xilinx XC3S400. Uses a FIFO and flashes some LEDs.
author: darius
date: Fri, 24 Feb 2006 14:01:25 +0000
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fifo.xco	Fri Feb 24 14:01:25 2006 +0000
@@ -0,0 +1,46 @@
+# BEGIN Project Options
+SET flowvendor = Foundation_iSE
+SET vhdlsim = True
+SET verilogsim = True
+SET workingdirectory = C:\Temp\Memec-test
+SET speedgrade = -5
+SET simulationfiles = Behavioral
+SET asysymbol = True
+SET addpads = False
+SET device = xc3s400
+SET implementationfiletype = Edif
+SET busformat = BusFormatAngleBracketNotRipped
+SET foundationsym = False
+SET package = pq208
+SET createndf = False
+SET designentry = VHDL
+SET devicefamily = spartan3
+SET formalverification = False
+SET removerpms = False
+# END Project Options
+# BEGIN Select
+SELECT Asynchronous_FIFO family Xilinx,_Inc. 6.1
+# END Select
+# BEGIN Parameters
+CSET create_rpm=false
+CSET read_acknowledge=false
+CSET almost_empty_flag=false
+CSET write_acknowledge=false
+CSET memory_type=block
+CSET read_acknowledge_sense=active_high
+CSET read_count_width=2
+CSET fifo_depth=15
+CSET component_name=fifo
+CSET write_count_width=2
+CSET write_count=false
+CSET read_count=false
+CSET write_error=false
+CSET read_error=false
+CSET read_error_sense=active_high
+CSET almost_full_flag=false
+CSET write_acknowledge_sense=active_high
+CSET write_error_sense=active_high
+CSET input_data_width=4
+# END Parameters
+GENERATE
+