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comparison fifo.veo @ 1:f88da01700da GSOFT-MEMEC-1-REL

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Initial import of test project for Memec 3SxLC board with Xilinx XC3S400. Uses a FIFO and flashes some LEDs.
author darius
date Fri, 24 Feb 2006 14:01:25 +0000
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0:7390b436dd20 1:f88da01700da
1 /*******************************************************************************
2 * This file is owned and controlled by Xilinx and must be used *
3 * solely for design, simulation, implementation and creation of *
4 * design files limited to Xilinx devices or technologies. Use *
5 * with non-Xilinx devices or technologies is expressly prohibited *
6 * and immediately terminates your license. *
7 * *
8 * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
9 * SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
10 * XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
11 * AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
12 * OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
13 * IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
14 * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
15 * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
16 * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
17 * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
18 * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
19 * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
20 * FOR A PARTICULAR PURPOSE. *
21 * *
22 * Xilinx products are not intended for use in life support *
23 * appliances, devices, or systems. Use in such applications are *
24 * expressly prohibited. *
25 * *
26 * (c) Copyright 1995-2006 Xilinx, Inc. *
27 * All rights reserved. *
28 *******************************************************************************/
29 // The following must be inserted into your Verilog file for this
30 // core to be instantiated. Change the instance name and port connections
31 // (in parentheses) to your own signal names.
32
33 //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
34 fifo YourInstanceName (
35 .din(din),
36 .wr_en(wr_en),
37 .wr_clk(wr_clk),
38 .rd_en(rd_en),
39 .rd_clk(rd_clk),
40 .ainit(ainit),
41 .dout(dout),
42 .full(full),
43 .empty(empty));
44
45 // INST_TAG_END ------ End INSTANTIATION Template ---------
46
47 // You must compile the wrapper file fifo.v when simulating
48 // the core, fifo. When compiling the wrapper file, be sure to
49 // reference the XilinxCoreLib Verilog simulation library. For detailed
50 // instructions, please refer to the "CORE Generator Help".
51