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annotate fifo.xco @ 1:f88da01700da GSOFT-MEMEC-1-REL

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Initial import of test project for Memec 3SxLC board with Xilinx XC3S400. Uses a FIFO and flashes some LEDs.
author darius
date Fri, 24 Feb 2006 14:01:25 +0000
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f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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1 # BEGIN Project Options
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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2 SET flowvendor = Foundation_iSE
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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3 SET vhdlsim = True
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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4 SET verilogsim = True
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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5 SET workingdirectory = C:\Temp\Memec-test
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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6 SET speedgrade = -5
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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7 SET simulationfiles = Behavioral
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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8 SET asysymbol = True
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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9 SET addpads = False
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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10 SET device = xc3s400
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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11 SET implementationfiletype = Edif
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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12 SET busformat = BusFormatAngleBracketNotRipped
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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13 SET foundationsym = False
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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14 SET package = pq208
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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15 SET createndf = False
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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16 SET designentry = VHDL
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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17 SET devicefamily = spartan3
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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18 SET formalverification = False
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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19 SET removerpms = False
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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20 # END Project Options
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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21 # BEGIN Select
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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22 SELECT Asynchronous_FIFO family Xilinx,_Inc. 6.1
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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23 # END Select
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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24 # BEGIN Parameters
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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25 CSET create_rpm=false
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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26 CSET read_acknowledge=false
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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27 CSET almost_empty_flag=false
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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28 CSET write_acknowledge=false
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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29 CSET memory_type=block
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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30 CSET read_acknowledge_sense=active_high
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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31 CSET read_count_width=2
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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32 CSET fifo_depth=15
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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33 CSET component_name=fifo
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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34 CSET write_count_width=2
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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35 CSET write_count=false
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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36 CSET read_count=false
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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37 CSET write_error=false
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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38 CSET read_error=false
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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39 CSET read_error_sense=active_high
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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40 CSET almost_full_flag=false
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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41 CSET write_acknowledge_sense=active_high
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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42 CSET write_error_sense=active_high
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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43 CSET input_data_width=4
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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44 # END Parameters
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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45 GENERATE
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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46