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comparison usb.c @ 41:5898fba6593c

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Add temperature control. - Split out console stuff to cons.[ch]. Set up stdio so we can use printf etc. - Use \r\n as the line terminator consistently. - Add OWGetTemp to get temperatures from a device. - Load/save settings in EEPROM, defaults loaded from flash. Nearly feature complete except you can't edit ROM IDs without a programming tool :) (To be fixed) Needs more testing.
author darius@inchoate.localdomain
date Sun, 06 Jul 2008 22:19:53 +0930
parents fed32b382de2
children
comparison
equal deleted inserted replaced
40:1061fdbdc44f 41:5898fba6593c
283 d12_read_cmd(D12_READ_CHIP_ID, buffer, 2); 283 d12_read_cmd(D12_READ_CHIP_ID, buffer, 2);
284 if (buffer[0] != 0x12 || buffer[1] != 0x10) { 284 if (buffer[0] != 0x12 || buffer[1] != 0x10) {
285 uart_putsP(PSTR("PDIUSBD12 does not appear to be present/working, chip ID = 0x")); 285 uart_putsP(PSTR("PDIUSBD12 does not appear to be present/working, chip ID = 0x"));
286 uart_puts_hex(buffer[0]); 286 uart_puts_hex(buffer[0]);
287 uart_puts_hex(buffer[1]); 287 uart_puts_hex(buffer[1]);
288 uart_putsP(PSTR(", expected 0x1210\n\r")); 288 uart_putsP(PSTR(", expected 0x1210\r\n"));
289 return; 289 return;
290 } 290 }
291 291
292 /* pull EE_Serial_Descriptor into RAM */ 292 /* pull EE_Serial_Descriptor into RAM */
293 eeprom_read_block(&Serial_Descriptor, &EE_Serial_Descriptor, EE_Serial_Descriptor.bLength); 293 eeprom_read_block(&Serial_Descriptor, &EE_Serial_Descriptor, EE_Serial_Descriptor.bLength);
331 331
332 /* Why do we get interrupts when this is 0? */ 332 /* Why do we get interrupts when this is 0? */
333 if (irq[0] == 0) 333 if (irq[0] == 0)
334 return; 334 return;
335 335
336 uart_putsP(PSTR("usb_intr() called\n\r")); 336 uart_putsP(PSTR("usb_intr() called\r\n"));
337 337
338 if (irq[0] & D12_INT_BUS_RESET) { 338 if (irq[0] & D12_INT_BUS_RESET) {
339 uart_putsP(PSTR("Bus reset\n\r")); 339 uart_putsP(PSTR("Bus reset\r\n"));
340 usb_init(); 340 usb_init();
341 return; 341 return;
342 } 342 }
343 343
344 if (irq[0] & D12_INT_SUSPEND) { 344 if (irq[0] & D12_INT_SUSPEND) {
345 uart_putsP(PSTR("Suspend change\n\r")); 345 uart_putsP(PSTR("Suspend change\r\n"));
346 } 346 }
347 347
348 if (irq[0] & D12_INT_EP0_IN) { 348 if (irq[0] & D12_INT_EP0_IN) {
349 d12_read_cmd(D12_READ_LAST_TRANSACTION + D12_ENDPOINT_EP0_IN, buffer, 1); 349 d12_read_cmd(D12_READ_LAST_TRANSACTION + D12_ENDPOINT_EP0_IN, buffer, 1);
350 if ((buffer[0] & D12_LAST_TRAN_ERRMSK) != 0) { 350 if ((buffer[0] & D12_LAST_TRAN_ERRMSK) != 0) {
351 uart_putsP(PSTR("EP0_IN error ")); 351 uart_putsP(PSTR("EP0_IN error "));
352 uart_puts_hex((buffer[0] & D12_LAST_TRAN_ERRMSK) >> 1); 352 uart_puts_hex((buffer[0] & D12_LAST_TRAN_ERRMSK) >> 1);
353 uart_putsP(PSTR("\n\r")); 353 uart_putsP(PSTR("\r\n"));
354 } 354 }
355 355
356 /* Handle any outgoing data for EP0 */ 356 /* Handle any outgoing data for EP0 */
357 d12_send_data_ep0(); 357 d12_send_data_ep0();
358 } 358 }
361 if (irq[0] & D12_INT_EP0_OUT) { 361 if (irq[0] & D12_INT_EP0_OUT) {
362 d12_read_cmd(D12_READ_LAST_TRANSACTION + D12_ENDPOINT_EP0_OUT, buffer, 1); 362 d12_read_cmd(D12_READ_LAST_TRANSACTION + D12_ENDPOINT_EP0_OUT, buffer, 1);
363 if ((buffer[0] & D12_LAST_TRAN_ERRMSK) != 0) { 363 if ((buffer[0] & D12_LAST_TRAN_ERRMSK) != 0) {
364 uart_putsP(PSTR("EP0_OUT error ")); 364 uart_putsP(PSTR("EP0_OUT error "));
365 uart_puts_hex((buffer[0] & D12_LAST_TRAN_ERRMSK) >> 1); 365 uart_puts_hex((buffer[0] & D12_LAST_TRAN_ERRMSK) >> 1);
366 uart_putsP(PSTR("\n\r")); 366 uart_putsP(PSTR("\r\n"));
367 } 367 }
368 368
369 if (buffer[0] & D12_LAST_TRAN_SETUP) 369 if (buffer[0] & D12_LAST_TRAN_SETUP)
370 d12_handle_setup(); 370 d12_handle_setup();
371 else { 371 else {
377 if (irq[0] & D12_INT_EP1_IN) { 377 if (irq[0] & D12_INT_EP1_IN) {
378 d12_read_cmd(D12_READ_LAST_TRANSACTION + D12_ENDPOINT_EP1_IN, buffer, 1); 378 d12_read_cmd(D12_READ_LAST_TRANSACTION + D12_ENDPOINT_EP1_IN, buffer, 1);
379 if ((buffer[0] & D12_LAST_TRAN_ERRMSK) != 0) { 379 if ((buffer[0] & D12_LAST_TRAN_ERRMSK) != 0) {
380 uart_putsP(PSTR("EP1_IN error ")); 380 uart_putsP(PSTR("EP1_IN error "));
381 uart_puts_hex((buffer[0] & D12_LAST_TRAN_ERRMSK) >> 1); 381 uart_puts_hex((buffer[0] & D12_LAST_TRAN_ERRMSK) >> 1);
382 uart_putsP(PSTR("\n\r")); 382 uart_putsP(PSTR("\r\n"));
383 } 383 }
384 384
385 /* Select endpoint */ 385 /* Select endpoint */
386 d12_read_cmd(D12_ENDPOINT_EP1_IN, buffer, 1); 386 d12_read_cmd(D12_ENDPOINT_EP1_IN, buffer, 1);
387 387
388 if (buffer[0] & 0x01) 388 if (buffer[0] & 0x01)
389 uart_putsP(PSTR("EP1_IN is full\n\r")); 389 uart_putsP(PSTR("EP1_IN is full\r\n"));
390 390
391 if (buffer[0] & 0x02) 391 if (buffer[0] & 0x02)
392 uart_putsP(PSTR("EP1_IN is stalled\n\r")); 392 uart_putsP(PSTR("EP1_IN is stalled\r\n"));
393 393
394 d12_write_endpt(D12_ENDPOINT_EP1_IN, NULL, 0); 394 d12_write_endpt(D12_ENDPOINT_EP1_IN, NULL, 0);
395 } 395 }
396 396
397 /* EPx_OUT is when we have gotten a packet from the host */ 397 /* EPx_OUT is when we have gotten a packet from the host */
398 if (irq[0] & D12_INT_EP1_OUT) { 398 if (irq[0] & D12_INT_EP1_OUT) {
399 d12_read_cmd(D12_READ_LAST_TRANSACTION + D12_ENDPOINT_EP1_OUT, buffer, 1); 399 d12_read_cmd(D12_READ_LAST_TRANSACTION + D12_ENDPOINT_EP1_OUT, buffer, 1);
400 if ((buffer[0] & D12_LAST_TRAN_ERRMSK) != 0) { 400 if ((buffer[0] & D12_LAST_TRAN_ERRMSK) != 0) {
401 uart_putsP(PSTR("EP1_OUT error ")); 401 uart_putsP(PSTR("EP1_OUT error "));
402 uart_puts_hex((buffer[0] & D12_LAST_TRAN_ERRMSK) >> 1); 402 uart_puts_hex((buffer[0] & D12_LAST_TRAN_ERRMSK) >> 1);
403 uart_putsP(PSTR("\n\r")); 403 uart_putsP(PSTR("\r\n"));
404 } 404 }
405 405
406 d12_receive_data_ep1(); 406 d12_receive_data_ep1();
407 } 407 }
408 408
409 if (irq[0] & D12_INT_EP2_IN) { 409 if (irq[0] & D12_INT_EP2_IN) {
410 d12_read_cmd(D12_READ_LAST_TRANSACTION + D12_ENDPOINT_EP2_IN, buffer, 1); 410 d12_read_cmd(D12_READ_LAST_TRANSACTION + D12_ENDPOINT_EP2_IN, buffer, 1);
411 if ((buffer[0] & D12_LAST_TRAN_ERRMSK) != 0) { 411 if ((buffer[0] & D12_LAST_TRAN_ERRMSK) != 0) {
412 uart_putsP(PSTR("EP2_IN error ")); 412 uart_putsP(PSTR("EP2_IN error "));
413 uart_puts_hex((buffer[0] & D12_LAST_TRAN_ERRMSK) >> 1); 413 uart_puts_hex((buffer[0] & D12_LAST_TRAN_ERRMSK) >> 1);
414 uart_putsP(PSTR("\n\r")); 414 uart_putsP(PSTR("\r\n"));
415 } 415 }
416 416
417 d12_send_data_ep2(); 417 d12_send_data_ep2();
418 } 418 }
419 419
420 if (irq[0] & D12_INT_EP2_OUT) { 420 if (irq[0] & D12_INT_EP2_OUT) {
421 d12_read_cmd(D12_READ_LAST_TRANSACTION + D12_ENDPOINT_EP2_OUT, buffer, 1); 421 d12_read_cmd(D12_READ_LAST_TRANSACTION + D12_ENDPOINT_EP2_OUT, buffer, 1);
422 if ((buffer[0] & D12_LAST_TRAN_ERRMSK) != 0) { 422 if ((buffer[0] & D12_LAST_TRAN_ERRMSK) != 0) {
423 uart_putsP(PSTR("EP2_OUT error ")); 423 uart_putsP(PSTR("EP2_OUT error "));
424 uart_puts_hex((buffer[0] & D12_LAST_TRAN_ERRMSK) >> 1); 424 uart_puts_hex((buffer[0] & D12_LAST_TRAN_ERRMSK) >> 1);
425 uart_putsP(PSTR("\n\r")); 425 uart_putsP(PSTR("\r\n"));
426 } 426 }
427 d12_receive_data_ep2(); 427 d12_receive_data_ep2();
428 } 428 }
429 } 429 }
430 430
703 ** Reset the micro by triggering the watchdog timer. 703 ** Reset the micro by triggering the watchdog timer.
704 ** 704 **
705 */ 705 */
706 void 706 void
707 reset(void) { 707 reset(void) {
708 uart_putsP(PSTR("Resetting!\n\r")); 708 uart_putsP(PSTR("Resetting!\r\n"));
709 _delay_us(1000); 709 _delay_us(1000);
710 710
711 /* Disable the interrupts */ 711 /* Disable the interrupts */
712 MCUCR = _BV(IVCE); 712 MCUCR = _BV(IVCE);
713 MCUCR = 0; 713 MCUCR = 0;
846 /* Select Endpoint */ 846 /* Select Endpoint */
847 d12_read_cmd(endpt, &status, 1); 847 d12_read_cmd(endpt, &status, 1);
848 if ((status & 0x01) != 0) { 848 if ((status & 0x01) != 0) {
849 uart_putsP(PSTR("Endpoint ")); 849 uart_putsP(PSTR("Endpoint "));
850 uart_puts_dec(endpt / 2, 0); 850 uart_puts_dec(endpt / 2, 0);
851 uart_putsP(PSTR(" IN is full..\n\r")); 851 uart_putsP(PSTR(" IN is full..\r\n"));
852 return; 852 return;
853 } 853 }
854 854
855 /* Write Header */ 855 /* Write Header */
856 d12_set_cmd(D12_WRITE_BUFFER); 856 d12_set_cmd(D12_WRITE_BUFFER);
962 /* Allow new packets to be accepted */ 962 /* Allow new packets to be accepted */
963 d12_write_cmd(D12_CLEAR_BUFFER, NULL, 0); 963 d12_write_cmd(D12_CLEAR_BUFFER, NULL, 0);
964 964
965 uart_putsP(PSTR("Got ")); 965 uart_putsP(PSTR("Got "));
966 uart_puts_dec(bytes, 0); 966 uart_puts_dec(bytes, 0);
967 uart_putsP(PSTR(" bytes from the host\n\r")); 967 uart_putsP(PSTR(" bytes from the host\r\n"));
968 968
969 parsebuf(packet2, D12_ENDPOINT_EP2_IN); 969 parsebuf(packet2, D12_ENDPOINT_EP2_IN);
970 970
971 } 971 }
972 972
1000 1000
1001 packetlen1 += bytes; 1001 packetlen1 += bytes;
1002 1002
1003 uart_putsP(PSTR("Got ")); 1003 uart_putsP(PSTR("Got "));
1004 uart_puts_dec(bytes, 0); 1004 uart_puts_dec(bytes, 0);
1005 uart_putsP(PSTR(" bytes from the host\n\r")); 1005 uart_putsP(PSTR(" bytes from the host\r\n"));
1006 1006
1007 /* Allow new packets to be accepted */ 1007 /* Allow new packets to be accepted */
1008 d12_write_cmd(D12_CLEAR_BUFFER, NULL, 0); 1008 d12_write_cmd(D12_CLEAR_BUFFER, NULL, 0);
1009 1009
1010 parsebuf(packet1, D12_ENDPOINT_EP1_IN); 1010 parsebuf(packet1, D12_ENDPOINT_EP1_IN);
1014 parsebuf(uint8_t *buffer, uint8_t ep) { 1014 parsebuf(uint8_t *buffer, uint8_t ep) {
1015 int i; 1015 int i;
1016 1016
1017 switch (buffer[0]) { 1017 switch (buffer[0]) {
1018 case 0x00: 1018 case 0x00:
1019 uart_putsP(PSTR("OWTouchReset()\n\r")); 1019 uart_putsP(PSTR("OWTouchReset()\r\n"));
1020 buffer[0] = OWTouchReset(); 1020 buffer[0] = OWTouchReset();
1021 d12_write_endpt(ep, buffer, 1); 1021 d12_write_endpt(ep, buffer, 1);
1022 break; 1022 break;
1023 1023
1024 case 0x01: 1024 case 0x01:
1025 uart_putsP(PSTR("OWFirst()\n\r")); 1025 uart_putsP(PSTR("OWFirst()\r\n"));
1026 buffer[0] = OWFirst(&buffer[1], 1, 0); 1026 buffer[0] = OWFirst(&buffer[1], 1, 0);
1027 for (i = 0; i < 9; i++) { 1027 for (i = 0; i < 9; i++) {
1028 uart_puts_hex(buffer[i + 1]); 1028 uart_puts_hex(buffer[i + 1]);
1029 uart_putsP(PSTR(" ")); 1029 uart_putsP(PSTR(" "));
1030 } 1030 }
1031 uart_putsP(PSTR("\n\r")); 1031 uart_putsP(PSTR("\r\n"));
1032 d12_write_endpt(ep, buffer, 9); 1032 d12_write_endpt(ep, buffer, 9);
1033 break; 1033 break;
1034 1034
1035 case 0x02: 1035 case 0x02:
1036 uart_putsP(PSTR("OWNext()\n\r")); 1036 uart_putsP(PSTR("OWNext()\r\n"));
1037 buffer[0] = OWNext(&buffer[1], 1, 0); 1037 buffer[0] = OWNext(&buffer[1], 1, 0);
1038 d12_write_endpt(ep, buffer, 9); 1038 d12_write_endpt(ep, buffer, 9);
1039 break; 1039 break;
1040 1040
1041 case 0x03: 1041 case 0x03:
1044 uart_puts_hex(buffer[i + 1]); 1044 uart_puts_hex(buffer[i + 1]);
1045 if (i != 7) 1045 if (i != 7)
1046 uart_putsP(PSTR(":")); 1046 uart_putsP(PSTR(":"));
1047 } 1047 }
1048 1048
1049 uart_putsP(PSTR("\n\r")); 1049 uart_putsP(PSTR("\r\n"));
1050 d12_write_endpt(ep, buffer, 9); 1050 d12_write_endpt(ep, buffer, 9);
1051 1051
1052 break; 1052 break;
1053 1053
1054 default: 1054 default:
1055 uart_putsP(PSTR("Unknown command on endpoint 1\n\r")); 1055 uart_putsP(PSTR("Unknown command on endpoint 1\r\n"));
1056 break; 1056 break;
1057 } 1057 }
1058 } 1058 }