Mercurial > ~darius > hgwebdir.cgi > tempctrl
annotate testavr.c @ 14:a9d493261c6c
- Add $Id$
- Rearrange slightly.
| author | darius |
|---|---|
| date | Sat, 17 Sep 2005 18:02:28 +0930 |
| parents | 2c03ec600dbc |
| children | 0940abdf2b9d |
| rev | line source |
|---|---|
| 0 | 1 /* |
|
9
7ed10c59ba06
Supply clock speed via the command line so 1wire-delay.h can use it.
darius
parents:
7
diff
changeset
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2 * Test various AVR bits and pieces |
|
7ed10c59ba06
Supply clock speed via the command line so 1wire-delay.h can use it.
darius
parents:
7
diff
changeset
|
3 * |
|
7ed10c59ba06
Supply clock speed via the command line so 1wire-delay.h can use it.
darius
parents:
7
diff
changeset
|
4 * $Id$ |
|
7ed10c59ba06
Supply clock speed via the command line so 1wire-delay.h can use it.
darius
parents:
7
diff
changeset
|
5 * |
| 0 | 6 * Copyright (c) 2004 |
| 7 * Daniel O'Connor <darius@dons.net.au>. All rights reserved. | |
| 8 * | |
| 9 * Redistribution and use in source and binary forms, with or without | |
| 10 * modification, are permitted provided that the following conditions | |
| 11 * are met: | |
| 12 * 1. Redistributions of source code must retain the above copyright | |
| 13 * notice, this list of conditions and the following disclaimer. | |
| 14 * 2. Redistributions in binary form must reproduce the above copyright | |
| 15 * notice, this list of conditions and the following disclaimer in the | |
| 16 * documentation and/or other materials provided with the distribution. | |
| 17 * | |
| 18 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND | |
| 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
| 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
| 21 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE | |
| 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
| 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
| 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
| 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
| 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |
| 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |
| 28 * SUCH DAMAGE. | |
| 29 */ | |
| 30 | |
| 31 #include <avr/io.h> | |
| 32 #include <avr/interrupt.h> | |
| 33 #include <avr/signal.h> | |
| 34 #include <avr/pgmspace.h> | |
| 35 #include <string.h> | |
| 4 | 36 #include <ctype.h> |
| 13 | 37 #include <stdlib.h> |
| 0 | 38 |
| 39 #include "1wire.h" | |
| 40 | |
| 41 #define UART_BAUD_SELECT(baudRate,xtalCpu) ((xtalCpu)/((baudRate)*16l)-1) | |
| 4 | 42 #define UART_BAUD_RATE 19200 |
| 0 | 43 |
| 44 void uart_putsP(const char *addr); | |
| 45 void uart_puts(const char *addr); | |
| 46 int uart_putc(char c); | |
| 4 | 47 int uart_getc(void); |
| 13 | 48 void uart_puts_dec(uint8_t a, uint8_t l); |
| 49 void uart_puts_hex(uint8_t a); | |
| 0 | 50 |
| 51 int | |
| 52 main(void) { | |
| 4 | 53 uint8_t ROM[8]; |
| 54 char cmdbuf[40]; | |
| 13 | 55 int8_t i, arg; |
| 0 | 56 |
| 57 cli(); | |
| 11 | 58 |
| 59 outp(0xfc, DDRC); | |
| 0 | 60 outp(0x00, PORTC); |
| 11 | 61 |
| 0 | 62 /* Init UART */ |
| 63 outp(UART_BAUD_SELECT(UART_BAUD_RATE,XTAL_CPU), UBRR); | |
| 64 | |
| 65 /* Enable receiver and transmitter. Turn on transmit interrupts */ | |
| 66 outp(BV(RXEN) | BV(TXEN), UCR); | |
| 67 | |
| 4 | 68 uart_putsP(PSTR("\n\r\n\r===============\n\r" |
| 69 "Inited!\n\r\n\r")); | |
| 70 | |
| 71 while (1) { | |
| 72 uart_putsP(PSTR("> ")); | |
| 73 i = 0; | |
| 74 while (1) { | |
| 75 cmdbuf[i] = tolower(uart_getc()); | |
| 76 if (cmdbuf[i] == '\n' || cmdbuf[i] == '\r') | |
| 77 break; | |
| 78 | |
| 79 /* Backspace */ | |
| 80 if (cmdbuf[i] == 010) { | |
| 81 if (i > 0) { | |
| 82 uart_putsP(PSTR("\010\040\010")); | |
| 83 i--; | |
| 84 } | |
| 85 continue; | |
| 86 } | |
| 0 | 87 |
| 4 | 88 /* Anything unprintable just ignore it */ |
| 89 if (!isprint(cmdbuf[i])) | |
| 90 continue; | |
| 91 | |
| 92 uart_putc(cmdbuf[i]); | |
| 93 i++; | |
| 94 if (i == sizeof(cmdbuf)) { | |
| 13 | 95 uart_putsP(PSTR("\n\rLine too long")); |
| 4 | 96 i = 0; |
| 13 | 97 break; |
| 4 | 98 } |
| 99 } | |
| 100 cmdbuf[i + 1] = '\0'; | |
| 101 uart_putsP(PSTR("\n\r")); | |
| 102 if (i == 0) | |
| 103 continue; | |
| 0 | 104 |
| 4 | 105 if (cmdbuf[0] == '?') { |
| 106 uart_putsP(PSTR("rs Reset and check for presence\n\r" | |
| 7 | 107 "sr Search the bus for ROMs\n\r" |
| 4 | 108 "re Read a bit\n\r" |
| 109 "rb Read a byte\n\r" | |
| 110 "wr bit Write a bit\n\r" | |
| 111 "wb byte Write a byte (hex)\n\r" | |
| 112 "wc cmd [ROMID] Write command\n\r" | |
| 13 | 113 "te ROMID Read the temperature from a DS1820\n\r")); |
| 11 | 114 |
| 4 | 115 continue; |
| 116 } | |
| 0 | 117 |
| 4 | 118 if (i < 2) |
| 119 goto badcmd; | |
| 120 | |
| 121 if (cmdbuf[0] == 'r' && cmdbuf[1] == 's') { | |
| 122 uart_putsP(PSTR("Resetting... ")); | |
| 123 | |
| 124 if (OWTouchReset() == 1) | |
| 10 | 125 uart_putsP(PSTR("No presense pulse found\n\r")); |
| 4 | 126 else |
| 10 | 127 uart_putsP(PSTR("Presense pulse found\n\r")); |
| 4 | 128 } else if (cmdbuf[0] == 'r' && cmdbuf[1] == 'e') { |
| 0 | 129 if (OWReadBit()) |
| 130 uart_putsP(PSTR("Read a 1\n\r")); | |
| 131 else | |
| 132 uart_putsP(PSTR("Read a 0\n\r")); | |
| 4 | 133 } else if (cmdbuf[0] == 'r' && cmdbuf[1] == 'b') { |
| 13 | 134 uart_putsP(PSTR("Read a 0x")); |
| 135 uart_puts_hex(OWReadByte()); | |
| 136 uart_putsP(PSTR("\n\r")); | |
| 4 | 137 } else if (cmdbuf[0] == 'w' && cmdbuf[1] == 'r') { |
| 13 | 138 arg = strtol(cmdbuf + 3, (char **)NULL, 10); |
| 4 | 139 OWWriteBit(arg); |
| 13 | 140 uart_putsP(PSTR("Wrote a ")); |
| 141 if (arg) | |
| 142 uart_putsP(PSTR("1\n\r")); | |
| 143 else | |
| 144 uart_putsP(PSTR("0\n\r")); | |
| 4 | 145 } else if (cmdbuf[0] == 'w' && cmdbuf[1] == 'b') { |
| 13 | 146 arg = (int)strtol(cmdbuf + 3, (char **)NULL, 16); |
| 147 OWWriteByte(arg); | |
| 148 } else if (cmdbuf[0] == 'w' && cmdbuf[1] == 'c') { | |
| 149 i = strlen(cmdbuf); | |
| 150 if (i < 5) { | |
| 151 uart_putsP(PSTR("No arguments\n\r")); | |
| 4 | 152 continue; |
| 153 } | |
| 154 | |
| 13 | 155 arg = (int)strtol(cmdbuf + 3, (char **)NULL, 16); |
| 156 if (arg == 0) { | |
| 157 uart_putsP(PSTR("Unparseable command\n\r")); | |
| 158 continue; | |
| 159 } | |
| 0 | 160 |
| 13 | 161 if (i == 5) { |
| 4 | 162 OWSendCmd(NULL, arg); |
| 13 | 163 continue; |
| 4 | 164 } |
| 165 | |
| 13 | 166 if (i < 29) { |
| 167 uart_putsP(PSTR("Can't parse ROM ID\n\r")); | |
| 168 continue; | |
| 169 } | |
| 170 for (i = 0; i < 8; i++) | |
| 171 ROM[i] = (int)strtol(cmdbuf + 6 + (3 * i), (char **)NULL, 16); | |
| 172 | |
| 173 OWSendCmd(ROM, arg); | |
| 4 | 174 } else if (cmdbuf[0] == 't' && cmdbuf[1] == 'e') { |
| 13 | 175 uint8_t crc, buf[9];; |
| 176 int8_t temp; | |
| 177 uint16_t tfrac; | |
| 4 | 178 |
| 13 | 179 if (strlen(cmdbuf) < 26) { |
| 4 | 180 uart_putsP(PSTR("Unable to parse ROM ID\n\r")); |
| 181 continue; | |
| 182 } | |
| 13 | 183 |
| 184 for (i = 0; i < 8; i++) | |
| 185 ROM[i] = (int)strtol(cmdbuf + 3 * (i + 1), (char **)NULL, 16); | |
| 186 | |
| 4 | 187 if (ROM[0] != OW_FAMILY_TEMP) { |
| 188 uart_putsP(PSTR("ROM specified isn't a temperature sensor\n\r")); | |
| 189 continue; | |
| 190 } | |
| 191 | |
| 192 OWSendCmd(ROM, OW_CONVERTT_CMD); | |
| 193 i = 0; | |
| 194 while (OWReadBit() == 0) { | |
| 195 i++; | |
| 196 } | |
| 197 OWSendCmd(ROM, OW_RD_SCR_CMD); | |
| 198 crc = 0; | |
| 199 for (i = 0; i < 9; i++) { | |
| 200 buf[i] = OWReadByte(); | |
| 201 if (i < 8) | |
| 202 OWCRC(buf[i], &crc); | |
| 203 } | |
| 204 | |
| 205 if (crc != buf[8]) { | |
| 13 | 206 uart_putsP(PSTR("CRC mismatch\n\r")); |
| 4 | 207 continue; |
| 208 } | |
| 209 | |
| 13 | 210 #if 0 |
| 211 uart_putsP(PSTR("temperature ")); | |
| 212 uart_puts_dec(temp >> 4, 0); | |
| 213 uart_putsP(PSTR(".")); | |
| 214 uart_puts_dec((temp << 12) / 6553, 0); | |
| 215 uart_putsP(PSTR("\n\r")); | |
| 216 #else | |
| 217 /* 0 Temperature LSB | |
| 218 * 1 Temperature MSB | |
| 219 * 2 Th | |
| 220 * 3 Tl | |
| 221 * 4 Reserved | |
| 222 * 5 Reserved | |
| 223 * 6 Count Remain | |
| 224 * 7 Count per C | |
| 225 * 8 CRC | |
| 226 */ | |
| 227 #if 0 | |
| 228 for (i = 0; i < 9; i++) { | |
| 229 uart_puts_dec(buf[i], 0); | |
| 230 uart_putsP(PSTR("\n\r")); | |
| 231 } | |
| 232 #endif | |
| 233 temp = buf[0]; | |
| 234 if (buf[0] & 0x01) | |
| 235 temp -= 256; | |
| 236 temp >>= 1; | |
| 237 | |
| 238 tfrac = buf[7] - buf[6]; | |
| 239 tfrac *= (uint16_t)100; | |
| 240 tfrac /= buf[7]; | |
| 241 tfrac += 75; | |
| 242 if (tfrac < 100) { | |
| 243 temp--; | |
| 244 } else { | |
| 245 tfrac -= 100; | |
| 246 } | |
| 247 | |
| 248 if (temp < 0){ | |
| 249 uart_putc('-'); | |
| 250 uart_puts_dec(-temp, 0); | |
| 251 } else | |
| 252 uart_puts_dec(temp, 0); | |
| 253 uart_putsP(PSTR(".")); | |
| 254 uart_puts_dec(tfrac, 1); | |
| 255 uart_putsP(PSTR("\n\r")); | |
| 256 | |
| 257 #endif | |
| 4 | 258 } else if (cmdbuf[0] == 's' && cmdbuf[1] == 'r') { |
| 259 memset(ROM, 0, 8); | |
| 10 | 260 |
| 261 i = OWFirst(ROM, 1, 0); | |
| 0 | 262 do { |
| 10 | 263 switch (i) { |
| 264 case OW_BADWIRE: | |
| 265 uart_putsP(PSTR("Presense pulse, but no module found, bad module/cabling?\n\r")); | |
| 266 break; | |
| 267 | |
| 268 case OW_NOPRESENCE: | |
| 269 uart_putsP(PSTR("No presense pulse found\n\r")); | |
| 270 break; | |
| 271 | |
| 272 case OW_BADCRC: | |
| 273 uart_putsP(PSTR("Bad CRC\n\r")); | |
| 274 break; | |
| 275 | |
| 276 case OW_NOMODULES: | |
| 277 case OW_FOUND: | |
| 278 break; | |
| 279 | |
| 280 default: | |
| 281 uart_putsP(PSTR("Unknown error from 1 wire library\n\r")); | |
| 282 break; | |
| 283 } | |
| 284 | |
| 285 if (i != OW_FOUND) | |
| 286 break; | |
| 13 | 287 |
| 288 for (i = 0; i < 7; i++) { | |
| 289 uart_puts_hex(ROM[i]); | |
| 290 uart_putc(':'); | |
| 291 } | |
| 292 uart_puts_hex(ROM[7]); | |
| 293 uart_putsP(PSTR("\n\r")); | |
| 10 | 294 |
| 295 i = OWNext(ROM, 1, 0); | |
| 296 } while (1); | |
| 4 | 297 } else { |
| 298 badcmd: | |
| 299 uart_putsP(PSTR("Unknown command, ? for a list\n\r")); | |
| 0 | 300 } |
| 301 | |
| 302 } | |
| 303 | |
| 304 return(0); | |
| 305 } | |
| 306 | |
| 307 int | |
| 308 uart_putc(char c) { | |
| 309 loop_until_bit_is_set(USR, UDRE); | |
| 310 outp(c, UDR); | |
| 311 | |
| 312 return(0); | |
| 313 } | |
| 314 | |
| 315 void | |
| 316 uart_putsP(const char *addr) { | |
| 317 char c; | |
| 318 | |
| 319 while ((c = PRG_RDB((unsigned short)addr++))) | |
| 320 uart_putc(c); | |
| 321 } | |
| 322 | |
| 323 void | |
| 324 uart_puts(const char *addr) { | |
| 325 while (*addr) | |
| 326 uart_putc(*addr++); | |
| 327 } | |
| 328 | |
| 13 | 329 void |
| 330 uart_puts_dec(uint8_t a, uint8_t l) { | |
| 331 char s[4]; | |
| 332 | |
| 333 if (l && a < 10) | |
| 334 uart_putsP(PSTR("0")); | |
| 335 uart_puts(utoa(a, s, 10)); | |
| 336 } | |
| 337 | |
| 338 void | |
| 339 uart_puts_hex(uint8_t a) { | |
| 340 char s[3]; | |
| 341 | |
| 342 if (a < 0x10) | |
| 343 uart_putc('0'); | |
| 344 | |
| 345 uart_puts(utoa(a, s, 16)); | |
| 346 } | |
| 347 | |
| 4 | 348 int |
| 0 | 349 uart_getc(void) { |
| 350 while (!(inp(USR) & 0x80)) | |
| 351 ; | |
| 352 | |
| 353 return (inp(UDR)); | |
| 354 } | |
| 4 | 355 |