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Initial commit of STM32 test code.
author Daniel O'Connor <darius@dons.net.au>
date Mon, 03 Oct 2011 21:19:15 +1030
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1 <html>
2
3 <head>
4 <title>CMSIS Changes</title>
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72 </style>
73 </head>
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75 <body>
76
77 <h1>Changes to CMSIS version V1.20</h1>
78
79 <hr>
80
81 <h2>1. Removed CMSIS Middelware packages</h2>
82 <p>
83 CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.
84 </p>
85
86 <h2>2. SystemFrequency renamed to SystemCoreClock</h2>
87 <p>
88 The variable name <strong>SystemCoreClock</strong> is more precise than <strong>SystemFrequency</strong>
89 because the variable holds the clock value at which the core is running.
90 </p>
91
92 <h2>3. Changed startup concept</h2>
93 <p>
94 The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit
95 from main) has the weakness that it does not work for controllers which need a already
96 configuerd clock system to configure the external memory controller.
97 </p>
98
99 <h3>Changed startup concept</h3>
100 <ul>
101 <li>
102 SystemInit() is called from startup file before <strong>premain</strong>.
103 </li>
104 <li>
105 <strong>SystemInit()</strong> configures the clock system and also configures
106 an existing external memory controller.
107 </li>
108 <li>
109 <strong>SystemInit()</strong> must not use global variables.
110 </li>
111 <li>
112 <strong>SystemCoreClock</strong> is initialized with a correct predefined value.
113 </li>
114 <li>
115 Additional function <strong>void SystemCoreClockUpdate (void)</strong> is provided.<br>
116 <strong>SystemCoreClockUpdate()</strong> updates the variable <strong>SystemCoreClock</strong>
117 and must be called whenever the core clock is changed.<br>
118 <strong>SystemCoreClockUpdate()</strong> evaluates the clock register settings and calculates
119 the current core clock.
120 </li>
121 </ul>
122
123
124 <h2>4. Advanced Debug Functions</h2>
125 <p>
126 ITM communication channel is only capable for OUT direction. To allow also communication for
127 IN direction a simple concept is provided.
128 </p>
129 <ul>
130 <li>
131 Global variable <strong>volatile int ITM_RxBuffer</strong> used for IN data.
132 </li>
133 <li>
134 Function <strong>int ITM_CheckChar (void)</strong> checks if a new character is available.
135 </li>
136 <li>
137 Function <strong>int ITM_ReceiveChar (void)</strong> retrieves the new character.
138 </li>
139 </ul>
140
141 <p>
142 For detailed explanation see file <strong>CMSIS debug support.htm</strong>.
143 </p>
144
145
146 <h2>5. Core Register Bit Definitions</h2>
147 <p>
148 Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
149 defines correspond with the Cortex-M Technical Reference Manual.
150 </p>
151 <p>
152 e.g. SysTick structure with bit definitions
153 </p>
154 <pre>
155 /** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
156 memory mapped structure for SysTick
157 @{
158 */
159 typedef struct
160 {
161 __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
162 __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
163 __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
164 __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
165 } SysTick_Type;
166
167 /* SysTick Control / Status Register Definitions */
168 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
169 #define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
170
171 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
172 #define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
173
174 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
175 #define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
176
177 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
178 #define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
179
180 /* SysTick Reload Register Definitions */
181 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
182 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
183
184 /* SysTick Current Register Definitions */
185 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
186 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
187
188 /* SysTick Calibration Register Definitions */
189 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
190 #define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
191
192 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
193 #define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
194
195 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
196 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
197 /*@}*/ /* end of group CMSIS_CM3_SysTick */</pre>
198
199 <h2>7. DoxyGen Tags</h2>
200 <p>
201 DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
202 using DoxyGen.
203 </p>
204
205 <h2>8. Folder Structure</h2>
206 <p>
207 The folder structure is changed to differentiate the single support packages.
208 </p>
209
210 <ul>
211 <li>CM0</li>
212 <li>CM3
213 <ul>
214 <li>CoreSupport</li>
215 <li>DeviceSupport</li>
216 <ul>
217 <li>Vendor
218 <ul>
219 <li>Device
220 <ul>
221 <li>Startup
222 <ul>
223 <li>Toolchain</li>
224 <li>Toolchain</li>
225 <li>...</li>
226 </ul>
227 </li>
228 </ul>
229 </li>
230 <li>Device</li>
231 <li>...</li>
232 </ul>
233 </li>
234 <li>Vendor</li>
235 <li>...</li>
236 </ul>
237 </li>
238 <li>Example
239 <ul>
240 <li>Toolchain
241 <ul>
242 <li>Device</li>
243 <li>Device</li>
244 <li>...</li>
245 </ul>
246 </li>
247 <li>Toolchain</li>
248 <li>...</li>
249 </ul>
250 </li>
251 </ul>
252 </li>
253
254 <li>Documentation</li>
255 </ul>
256
257 <h2>9. Open Points</h2>
258 <p>
259 Following points need to be clarified and solved:
260 </p>
261 <ul>
262 <li>
263 <p>
264 Equivalent C and Assembler startup files.
265 </p>
266 <p>
267 Is there a need for having C startup files although assembler startup files are
268 very efficient and do not need to be changed?
269 <p/>
270 </li>
271 <li>
272 <p>
273 Placing of HEAP in external RAM.
274 </p>
275 <p>
276 It must be possible to place HEAP in external RAM if the device supports an
277 external memory controller.
278 </p>
279 </li>
280 <li>
281 <p>
282 Placing of STACK /HEAP.
283 </p>
284 <p>
285 STACK should always be placed at the end of internal RAM.
286 </p>
287 <p>
288 If HEAP is placed in internal RAM than it should be placed after RW ZI section.
289 </p>
290 </li>
291 <li>
292 <p>
293 Removing core_cm3.c and core_cm0.c.
294 </p>
295 <p>
296 On a long term the functions in core_cm3.c and core_cm0.c must be replaced with
297 appropriate compiler intrinsics.
298 </p>
299 </li>
300 </ul>
301
302
303 <h2>10. Limitations</h2>
304 <p>
305 The following limitations are not covered with the current CMSIS version:
306 </p>
307 <ul>
308 <li>
309 No <strong>C startup files</strong> for ARM toolchain are provided.
310 </li>
311 <li>
312 No <strong>C startup files</strong> for GNU toolchain are provided.
313 </li>
314 <li>
315 No <strong>C startup files</strong> for IAR toolchain are provided.
316 </li>
317 <li>
318 No <strong>Tasking</strong> projects are provided yet.
319 </li>
320 </ul>