--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/lcd.c	Sun Jan 01 11:01:13 2012 +1030
@@ -0,0 +1,122 @@
+/*
+ * Example code (I think)
+ * ~/projects/STM32Strive/奋斗STM32开发板例程/奋斗STM32开发板例程/奋斗STM32开发板MINI/STM32奋斗版ucOS II V2.86 uCGUI 3.9 DEMO-V2/STM32奋斗版ucOS II V2.86 uCGUI 3.9 DEMO
+ *
+ * Schematics
+ * Main board ~/Downloads/Strive\ Mini\ STM32\ Schematic.pdf 
+ * LCD board ~/Downloads/Strive Mini LCD STM32 Schematic.pdf
+ * MCU reference manual
+ * ~/Downloads/CD00171190.pdf
+ * MCU Data sheet (pinout)
+ * ~/Downloads/CD00191185.pdf
+ * LCD data sheet
+ * 
+ */
+/*	LCD board	MCU
+  1	VCC		
+  2	TC_SCK		PA5/SPI1_SCK
+  3	GND		
+  4	TC_CS		PB7/SPI1_CS3
+  5	RST		PE1 FSMC_NBL1? (unlikely)
+  6	TC_DIN		PA7/SPI1_MOSI
+  7	nOE		PD4/FSMC_nOE
+  8    	TC_DOUT		PA6/SPI1_MISO
+  9	nWR		PD5/FSMC_nWE
+  10	TC_INT		PB6
+  11	CS		PD7/FSMC_NE1/FSMC_NCE2
+  12	NC		
+  13	RS		PD11/FSMC_A16
+  14	NC		
+  15	D7		PE10/FSMC_D7
+  16	NC		
+  17	D6		PE9/FSMC_D6
+  18	NC		
+  19	D3		PD1/FSMC_D3
+  20	D13		PD8/FSMC_D13
+  21	D5		PE8/FSMC_D5
+  22	D12		PE15/FSMC_D12
+  23	D4		PE7/FSMC_D4
+  24	GND		
+  25	NC		
+  26	D11		PE14/FSMC_D11
+  27	D2		PD0/FSMC_D2
+  28	D10		PE13/FSMC_D10
+  29	D1		PD15/FSMC_D1
+  30	D9		PE12/FSMC_D9
+  31	D0		PD14/FSMC_D0
+  32	D14		PD9/FSMC_D9
+  33	NC		
+  34	D8		PE11/FSMC_D8
+  35	NC		
+  36	NC		
+  37	NC		
+  38	LCD_PWM		PD13/TIM4_CH2
+  39	NC		
+  40	D15		PD10/FSMC_D15
+*/
+
+#include "stm32f10x.h"
+#include "lcd.h"
+
+void
+LCD_init(void) {
+    GPIO_InitTypeDef			GPIO_InitStructure;
+    FSMC_NORSRAMInitTypeDef		FSMC_NORSRAMInitStructure;
+    FSMC_NORSRAMTimingInitTypeDef	p;
+
+    /* Configures LCD Control lines (FSMC Pins) in alternate function Push-Pull mode.
+     *
+     * PD0(D2), PD1(D3), PD4(NOE), PD5(NWE), PD7(NE1/CS), PD8(D13), PD9(D14),
+     * PD10(D15), PD11(A16/RS) PD14(D0), PD15(D1)
+     */
+    GPIO_InitStructure.GPIO_Pin = (GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_7 |
+				   GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_14 | GPIO_Pin_15);
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+    /* PE7(D4), PE8(D5), PE9(D6), PE10(D7), PE11(D8), PE12(D9), PE13(D10),
+     * PE14(D11), PE15(D12)
+     */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | 
+    GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
+    GPIO_Init(GPIOE, &GPIO_InitStructure);
+
+    /* Configures the Parallel interface (FSMC) for LCD (Parallel mode) */
+    /* FSMC_Bank1_NORSRAM4 timing configuration */
+    p.FSMC_AddressSetupTime = 1;
+    p.FSMC_AddressHoldTime = 0;
+    p.FSMC_DataSetupTime = 2;
+    p.FSMC_BusTurnAroundDuration = 0;
+    p.FSMC_CLKDivision = 0;
+    p.FSMC_DataLatency = 0;
+    p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+    /* FSMC_Bank1_NORSRAM4 configured as follows:
+       - Data/Address MUX = Disable
+       - Memory Type = SRAM
+       - Data Width = 16bit
+       - Write Operation = Enable
+       - Extended Mode = Disable
+       - Asynchronous Wait = Disable */
+    FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM4;
+    FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+    FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
+    FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+    FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+    FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+    FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+    FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+    FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+    FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+    FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+    FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+    FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+    FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+    FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+
+    FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);  
+
+    /* Enable FSMC_Bank1_NORSRAM4 */
+    FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE);
+}