diff hw.c @ 8:58d76cf522ff

Split out code into separate files.
author Daniel O'Connor <darius@dons.net.au>
date Sat, 04 Feb 2012 13:29:31 +1030
parents
children 0b75cff7c570
line wrap: on
line diff
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hw.c	Sat Feb 04 13:29:31 2012 +1030
@@ -0,0 +1,263 @@
+#include <stdint.h>
+#include "stm32f10x.h"
+#include "lcd.h"
+
+static void	hw_port_cfg(void);
+
+
+void hw_init(void) {
+    hw_port_cfg();
+    lcd_init();
+    lcd_setpwm(1000);
+}
+
+static void
+hw_port_cfg(void) {
+    GPIO_InitTypeDef			GPIO_InitStructure;
+    USART_InitTypeDef USART_InitStructure;
+    SPI_InitTypeDef			SPI_InitStructure;
+    FSMC_NORSRAMInitTypeDef		FSMC_NORSRAMInitStructure;
+    FSMC_NORSRAMTimingInitTypeDef	p;
+    TIM_TimeBaseInitTypeDef		TIM_TimeBaseStructure;
+    
+    /* RTC stuff */
+    /* Enable PWR and BKP clocks */
+    RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
+
+    /* Allow access to BKP Domain */
+    PWR_BackupAccessCmd(ENABLE);
+
+    /* Reset Backup Domain
+     *
+     * This resets the RTC etc back to 0 so probably only useful under user command
+     BKP_DeInit();
+    */
+
+    /* Enable Low Speed External clock */
+    RCC_LSEConfig(RCC_LSE_ON);
+
+    /* Wait till LSE is ready */
+    while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)
+	;
+
+    /* Select LSE as RTC Clock Source */
+    RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
+
+    /* Enable RTC Clock */
+    RCC_RTCCLKCmd(ENABLE);
+
+    /* Wait for RTC registers synchronization */
+    RTC_WaitForSynchro();
+
+    /* Wait until last write operation on RTC registers has finished */
+    RTC_WaitForLastTask();
+
+    /* Wait until last write operation on RTC registers has finished */
+    RTC_WaitForLastTask();
+
+    /* Set RTC prescaler: set RTC period to 1sec */
+    RTC_SetPrescaler(32767); /* RTC period = RTCCLK/RTC_PR = (32.768 KHz)/(32767+1) */
+
+    /* Wait until last write operation on RTC registers has finished */
+    RTC_WaitForLastTask();
+
+    /* Clock setup */
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
+
+    /* Port configuration */
+    /* Configure USART1 TX (PA.09) as alternate function push-pull */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+    /* Configure USART1 RX (PA.10) as input floating */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+    /* Enable GPIOB clock */
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
+
+    /* Configure PB5 as output push-pull for LED */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+    GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+    /* Configure PB15 as input pull-up push-pull for push button */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+    GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+    /* USART configuration */
+    /* USART1 - 115200 8n1, no flow control TX & RX enabled */
+    USART_InitStructure.USART_BaudRate = 115200;
+    USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+    USART_InitStructure.USART_StopBits = USART_StopBits_1;
+    USART_InitStructure.USART_Parity = USART_Parity_No;
+    USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+    USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+    USART_Init(USART1, &USART_InitStructure);
+
+    /* Enable interrupts on receive data */
+    USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);
+
+    /* Enable USART */
+    USART_Cmd(USART1, ENABLE);
+
+    /* Enable FSMC clock */
+    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
+
+    /* Enable alternate function IO clock */
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
+
+    /* Enable GPIOD clock */
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE);
+
+    /* Enable GPIOD clock */
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE, ENABLE);
+
+    /* Configures LCD Control lines (FSMC Pins) in alternate function Push-Pull mode.
+     *
+     * PD0(D2), PD1(D3), PD4(NOE), PD5(NWE), PD7(NE1/CS), PD8(D13), PD9(D14),
+     * PD10(D15), PD11(A16/RS) PD14(D0), PD15(D1)
+     */
+    GPIO_InitStructure.GPIO_Pin = (GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_7 |
+				   GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | 
+				   GPIO_Pin_14 | GPIO_Pin_15);
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+    /* PE7(D4), PE8(D5), PE9(D6), PE10(D7), PE11(D8), PE12(D9), PE13(D10),
+     * PE14(D11), PE15(D12)
+     */
+    GPIO_InitStructure.GPIO_Pin = (GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | 
+				   GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
+				   GPIO_Pin_15);
+    GPIO_Init(GPIOE, &GPIO_InitStructure);
+
+    /* Configure backlight control (PD13/FSMC_A18 remapped to TIM4_CH2) */
+    /* Enable TIM4 clock */
+    RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
+
+    /* Enable timer function
+     * Note source clock is SYSCLK / 2 = 36MHz
+     */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+    /* Remap TIM4_CH2 to PD13 */
+    GPIO_PinRemapConfig(GPIO_Remap_TIM4, ENABLE);
+    
+    /* Reset TIM4 */
+    TIM_DeInit(TIM4);
+
+    /* Time Base configuration */
+    TIM_TimeBaseStructure.TIM_Period = 999;
+    TIM_TimeBaseStructure.TIM_Prescaler = 0;
+    TIM_TimeBaseStructure.TIM_ClockDivision = 0;
+    TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Down;
+
+    TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
+
+    /* Enable timer */
+    TIM_OC2PreloadConfig(TIM4, TIM_OCPreload_Enable);
+    TIM_ARRPreloadConfig(TIM4, ENABLE);
+    TIM_Cmd(TIM4, ENABLE);
+
+    /* Configure reset pin (PE1) as GPIO out PP */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+    GPIO_Init(GPIOE, &GPIO_InitStructure);
+
+    /* Configures the Parallel interface (FSMC) for LCD (Parallel mode) */
+    /* Timing configuration */
+    p.FSMC_AddressSetupTime = 5;
+    p.FSMC_AddressHoldTime = 5;
+    p.FSMC_DataSetupTime = 5;
+    p.FSMC_BusTurnAroundDuration = 0;
+    p.FSMC_CLKDivision = 0;
+    p.FSMC_DataLatency = 0;
+    p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+    /* FSMC_Bank1_NORSRAM1 configured as follows:
+       - Data/Address MUX = Disable
+       - Memory Type = SRAM
+       - Data Width = 16bit
+       - Write Operation = Enable
+       - Extended Mode = Disable
+       - Asynchronous Wait = Disable */
+    FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM1;
+    FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+    FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
+    FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+    FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+    FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+    FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+    FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+    FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+    FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+    FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+    FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+    FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+    FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+    FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+    FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);  
+
+    /* Enable FSMC_Bank1_NORSRAM1 */
+    FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE);
+
+    /* Configure touch screen controller
+     *
+     * Connected to SPI1 which is shared with the AT45DB161D.
+     *
+     * The touch screen is selected with PB7.
+     * The flash chip is selected with PA4.
+     */
+
+    /* Enable SPI1 clock */
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
+
+    /* Configure MOSI, MISO and SCLK as alternate function PP */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+    /* Configure flash chip select pin (PA4) as GPIO out PP */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+    /* Configure touch chip select pin (PB7) as GPIO out PP */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+    GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+    /* De-select touch & flash */
+    GPIO_SetBits(GPIOA, GPIO_Pin_4);
+    GPIO_SetBits(GPIOB, GPIO_Pin_7);
+    
+    /* SPI1 Config */
+    SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+    SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+    SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
+    SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
+    SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
+    SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+    SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64;
+    SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+    SPI_InitStructure.SPI_CRCPolynomial = 7;
+    SPI_Init(SPI1, &SPI_InitStructure);
+
+    /* SPI1 enable */
+    SPI_Cmd(SPI1, ENABLE);  
+}