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comparison libs/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_sram.c @ 0:c59513fd84fb

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Initial commit of STM32 test code.
author Daniel O'Connor <darius@dons.net.au>
date Mon, 03 Oct 2011 21:19:15 +1030
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1 /**
2 ******************************************************************************
3 * @file stm3210e_eval_fsmc_sram.c
4 * @author MCD Application Team
5 * @version V4.5.0
6 * @date 07-March-2011
7 * @brief This file provides a set of functions needed to drive the
8 * IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board.
9 ******************************************************************************
10 * @attention
11 *
12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 *
19 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
20 ******************************************************************************
21 */
22
23 /* Includes ------------------------------------------------------------------*/
24 #include "stm3210e_eval_fsmc_sram.h"
25
26 /** @addtogroup Utilities
27 * @{
28 */
29
30 /** @addtogroup STM32_EVAL
31 * @{
32 */
33
34 /** @addtogroup STM3210E_EVAL
35 * @{
36 */
37
38 /** @addtogroup STM3210E_EVAL_FSMC_SRAM
39 * @brief This file provides a set of functions needed to drive the
40 * IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board.
41 * @{
42 */
43
44 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Types
45 * @{
46 */
47 /**
48 * @}
49 */
50
51
52 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Defines
53 * @{
54 */
55 /**
56 * @brief FSMC Bank 1 NOR/SRAM3
57 */
58 #define Bank1_SRAM3_ADDR ((uint32_t)0x68000000)
59 /**
60 * @}
61 */
62
63
64 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Macros
65 * @{
66 */
67 /**
68 * @}
69 */
70
71
72 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Variables
73 * @{
74 */
75 /**
76 * @}
77 */
78
79
80 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Function_Prototypes
81 * @{
82 */
83 /**
84 * @}
85 */
86
87
88 /** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Functions
89 * @{
90 */
91
92 /**
93 * @brief Configures the FSMC and GPIOs to interface with the SRAM memory.
94 * This function must be called before any write/read operation
95 * on the SRAM.
96 * @param None
97 * @retval None
98 */
99 void SRAM_Init(void)
100 {
101 FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
102 FSMC_NORSRAMTimingInitTypeDef p;
103 GPIO_InitTypeDef GPIO_InitStructure;
104
105 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE |
106 RCC_APB2Periph_GPIOF, ENABLE);
107
108 /*-- GPIO Configuration ------------------------------------------------------*/
109 /*!< SRAM Data lines configuration */
110 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
111 GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
112 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
113 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
114 GPIO_Init(GPIOD, &GPIO_InitStructure);
115
116 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
117 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
118 GPIO_Pin_15;
119 GPIO_Init(GPIOE, &GPIO_InitStructure);
120
121 /*!< SRAM Address lines configuration */
122 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
123 GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
124 GPIO_Pin_14 | GPIO_Pin_15;
125 GPIO_Init(GPIOF, &GPIO_InitStructure);
126
127 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
128 GPIO_Pin_4 | GPIO_Pin_5;
129 GPIO_Init(GPIOG, &GPIO_InitStructure);
130
131 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
132 GPIO_Init(GPIOD, &GPIO_InitStructure);
133
134 /*!< NOE and NWE configuration */
135 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 |GPIO_Pin_5;
136 GPIO_Init(GPIOD, &GPIO_InitStructure);
137
138 /*!< NE3 configuration */
139 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
140 GPIO_Init(GPIOG, &GPIO_InitStructure);
141
142 /*!< NBL0, NBL1 configuration */
143 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
144 GPIO_Init(GPIOE, &GPIO_InitStructure);
145
146 /*-- FSMC Configuration ------------------------------------------------------*/
147 p.FSMC_AddressSetupTime = 0;
148 p.FSMC_AddressHoldTime = 0;
149 p.FSMC_DataSetupTime = 1;
150 p.FSMC_BusTurnAroundDuration = 0;
151 p.FSMC_CLKDivision = 0;
152 p.FSMC_DataLatency = 0;
153 p.FSMC_AccessMode = FSMC_AccessMode_A;
154
155 FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
156 FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
157 FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
158 FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
159 FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
160 FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
161 FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
162 FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
163 FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
164 FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
165 FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
166 FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
167 FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
168 FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
169 FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
170
171 FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
172
173 /*!< Enable FSMC Bank1_SRAM Bank */
174 FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
175 }
176
177 /**
178 * @brief Writes a Half-word buffer to the FSMC SRAM memory.
179 * @param pBuffer : pointer to buffer.
180 * @param WriteAddr : SRAM memory internal address from which the data will be
181 * written.
182 * @param NumHalfwordToWrite : number of half-words to write.
183 * @retval None
184 */
185 void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
186 {
187 for(; NumHalfwordToWrite != 0; NumHalfwordToWrite--) /*!< while there is data to write */
188 {
189 /*!< Transfer data to the memory */
190 *(uint16_t *) (Bank1_SRAM3_ADDR + WriteAddr) = *pBuffer++;
191
192 /*!< Increment the address*/
193 WriteAddr += 2;
194 }
195 }
196
197 /**
198 * @brief Reads a block of data from the FSMC SRAM memory.
199 * @param pBuffer : pointer to the buffer that receives the data read from the
200 * SRAM memory.
201 * @param ReadAddr : SRAM memory internal address to read from.
202 * @param NumHalfwordToRead : number of half-words to read.
203 * @retval None
204 */
205 void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
206 {
207 for(; NumHalfwordToRead != 0; NumHalfwordToRead--) /*!< while there is data to read */
208 {
209 /*!< Read a half-word from the memory */
210 *pBuffer++ = *(__IO uint16_t*) (Bank1_SRAM3_ADDR + ReadAddr);
211
212 /*!< Increment the address*/
213 ReadAddr += 2;
214 }
215 }
216
217 /**
218 * @}
219 */
220
221 /**
222 * @}
223 */
224
225 /**
226 * @}
227 */
228
229 /**
230 * @}
231 */
232
233 /**
234 * @}
235 */
236
237 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/