Mercurial > ~darius > hgwebdir.cgi > stm32temp

comparison libs/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.c @ 0:c59513fd84fb

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Initial commit of STM32 test code.
author Daniel O'Connor <darius@dons.net.au>
date Mon, 03 Oct 2011 21:19:15 +1030
parents
children
comparison
equal deleted inserted replaced
-1:000000000000 0:c59513fd84fb
1 /**
2 ******************************************************************************
3 * @file stm3210e_eval_fsmc_nor.c
4 * @author MCD Application Team
5 * @version V4.5.0
6 * @date 07-March-2011
7 * @brief This file provides a set of functions needed to drive the M29W128FL,
8 * M29W128GL and S29GL128P NOR memories mounted on STM3210E-EVAL board.
9 ******************************************************************************
10 * @attention
11 *
12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 *
19 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
20 ******************************************************************************
21 */
22
23 /* Includes ------------------------------------------------------------------*/
24 #include "stm3210e_eval_fsmc_nor.h"
25
26 /** @addtogroup Utilities
27 * @{
28 */
29
30 /** @addtogroup STM32_EVAL
31 * @{
32 */
33
34 /** @addtogroup STM3210E_EVAL
35 * @{
36 */
37
38 /** @addtogroup STM3210E_EVAL_FSMC_NOR
39 * @brief This file provides a set of functions needed to drive the M29W128FL,
40 * M29W128GL and S29GL128P NOR memories mounted on STM3210E-EVAL board.
41 * @{
42 */
43
44 /** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Types
45 * @{
46 */
47 /**
48 * @}
49 */
50
51 /** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Defines
52 * @{
53 */
54 /**
55 * @brief FSMC Bank 1 NOR/SRAM2
56 */
57 #define Bank1_NOR2_ADDR ((uint32_t)0x64000000)
58
59 /* Delay definition */
60 #define BlockErase_Timeout ((uint32_t)0x00A00000)
61 #define ChipErase_Timeout ((uint32_t)0x30000000)
62 #define Program_Timeout ((uint32_t)0x00001400)
63 /**
64 * @}
65 */
66
67
68 /** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Macros
69 * @{
70 */
71 #define ADDR_SHIFT(A) (Bank1_NOR2_ADDR + (2 * (A)))
72 #define NOR_WRITE(Address, Data) (*(__IO uint16_t *)(Address) = (Data))
73 /**
74 * @}
75 */
76
77
78 /** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Variables
79 * @{
80 */
81 /**
82 * @}
83 */
84
85
86 /** @defgroupSTM3210E_EVAL_FSMC_NOR_Private_Function_Prototypes
87 * @{
88 */
89 /**
90 * @}
91 */
92
93
94 /** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Functions
95 * @{
96 */
97
98 /**
99 * @brief Configures the FSMC and GPIOs to interface with the NOR memory.
100 * This function must be called before any write/read operation
101 * on the NOR.
102 * @param None
103 * @retval None
104 */
105 void NOR_Init(void)
106 {
107 FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
108 FSMC_NORSRAMTimingInitTypeDef p;
109 GPIO_InitTypeDef GPIO_InitStructure;
110
111 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
112 RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
113
114 /*-- GPIO Configuration ------------------------------------------------------*/
115 /*!< NOR Data lines configuration */
116 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
117 GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
118 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
119 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
120 GPIO_Init(GPIOD, &GPIO_InitStructure);
121
122 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
123 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
124 GPIO_Pin_14 | GPIO_Pin_15;
125 GPIO_Init(GPIOE, &GPIO_InitStructure);
126
127 /*!< NOR Address lines configuration */
128 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
129 GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
130 GPIO_Pin_14 | GPIO_Pin_15;
131 GPIO_Init(GPIOF, &GPIO_InitStructure);
132
133 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 |
134 GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5;
135 GPIO_Init(GPIOG, &GPIO_InitStructure);
136
137 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
138 GPIO_Init(GPIOD, &GPIO_InitStructure);
139
140 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6;
141 GPIO_Init(GPIOE, &GPIO_InitStructure);
142
143 /*!< NOE and NWE configuration */
144 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
145 GPIO_Init(GPIOD, &GPIO_InitStructure);
146
147 /*!< NE2 configuration */
148 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
149 GPIO_Init(GPIOG, &GPIO_InitStructure);
150
151 /*!< Configure PD6 for NOR memory Ready/Busy signal */
152 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
153 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
154 GPIO_Init(GPIOD, &GPIO_InitStructure);
155
156 /*-- FSMC Configuration ----------------------------------------------------*/
157 p.FSMC_AddressSetupTime = 0x02;
158 p.FSMC_AddressHoldTime = 0x00;
159 p.FSMC_DataSetupTime = 0x05;
160 p.FSMC_BusTurnAroundDuration = 0x00;
161 p.FSMC_CLKDivision = 0x00;
162 p.FSMC_DataLatency = 0x00;
163 p.FSMC_AccessMode = FSMC_AccessMode_B;
164
165 FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
166 FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
167 FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR;
168 FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
169 FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
170 FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
171 FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
172 FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
173 FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
174 FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
175 FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
176 FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
177 FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
178 FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
179 FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
180
181 FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
182
183 /*!< Enable FSMC Bank1_NOR Bank */
184 FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
185 }
186
187 /**
188 * @brief Reads NOR memory's Manufacturer and Device Code.
189 * @param NOR_ID: pointer to a NOR_IDTypeDef structure which will hold the
190 * Manufacturer and Device Code.
191 * @retval None
192 */
193 void NOR_ReadID(NOR_IDTypeDef* NOR_ID)
194 {
195 NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
196 NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
197 NOR_WRITE(ADDR_SHIFT(0x0555), 0x0090);
198
199 NOR_ID->Manufacturer_Code = *(__IO uint16_t *) ADDR_SHIFT(0x0000);
200 NOR_ID->Device_Code1 = *(__IO uint16_t *) ADDR_SHIFT(0x0001);
201 NOR_ID->Device_Code2 = *(__IO uint16_t *) ADDR_SHIFT(0x000E);
202 NOR_ID->Device_Code3 = *(__IO uint16_t *) ADDR_SHIFT(0x000F);
203 }
204
205 /**
206 * @brief Erases the specified Nor memory block.
207 * @param BlockAddr: address of the block to erase.
208 * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
209 * or NOR_TIMEOUT
210 */
211 NOR_Status NOR_EraseBlock(uint32_t BlockAddr)
212 {
213 NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
214 NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
215 NOR_WRITE(ADDR_SHIFT(0x0555), 0x0080);
216 NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
217 NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
218 NOR_WRITE((Bank1_NOR2_ADDR + BlockAddr), 0x30);
219
220 return (NOR_GetStatus(BlockErase_Timeout));
221 }
222
223 /**
224 * @brief Erases the entire chip.
225 * @param None
226 * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
227 * or NOR_TIMEOUT
228 */
229 NOR_Status NOR_EraseChip(void)
230 {
231 NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
232 NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
233 NOR_WRITE(ADDR_SHIFT(0x0555), 0x0080);
234 NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
235 NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
236 NOR_WRITE(ADDR_SHIFT(0x0555), 0x0010);
237
238 return (NOR_GetStatus(ChipErase_Timeout));
239 }
240
241 /**
242 * @brief Writes a half-word to the NOR memory.
243 * @param WriteAddr: NOR memory internal address to write to.
244 * @param Data: Data to write.
245 * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
246 * or NOR_TIMEOUT
247 */
248 NOR_Status NOR_WriteHalfWord(uint32_t WriteAddr, uint16_t Data)
249 {
250 NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
251 NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
252 NOR_WRITE(ADDR_SHIFT(0x0555), 0x00A0);
253 NOR_WRITE((Bank1_NOR2_ADDR + WriteAddr), Data);
254
255 return (NOR_GetStatus(Program_Timeout));
256 }
257
258 /**
259 * @brief Writes a half-word buffer to the FSMC NOR memory.
260 * @param pBuffer: pointer to buffer.
261 * @param WriteAddr: NOR memory internal address from which the data will be
262 * written.
263 * @param NumHalfwordToWrite: number of Half words to write.
264 * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
265 * or NOR_TIMEOUT
266 */
267 NOR_Status NOR_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
268 {
269 NOR_Status status = NOR_ONGOING;
270
271 do
272 {
273 /*!< Transfer data to the memory */
274 status = NOR_WriteHalfWord(WriteAddr, *pBuffer++);
275 WriteAddr = WriteAddr + 2;
276 NumHalfwordToWrite--;
277 }
278 while((status == NOR_SUCCESS) && (NumHalfwordToWrite != 0));
279
280 return (status);
281 }
282
283 /**
284 * @brief Writes a half-word buffer to the FSMC NOR memory. This function
285 * must be used only with S29GL128P NOR memory.
286 * @param pBuffer: pointer to buffer.
287 * @param WriteAddr: NOR memory internal address from which the data will be
288 * written.
289 * @param NumHalfwordToWrite: number of Half words to write.
290 * The maximum allowed value is 32 Half words (64 bytes).
291 * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
292 * or NOR_TIMEOUT
293 */
294 NOR_Status NOR_ProgramBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
295 {
296 uint32_t lastloadedaddress = 0x00;
297 uint32_t currentaddress = 0x00;
298 uint32_t endaddress = 0x00;
299
300 /*!< Initialize variables */
301 currentaddress = WriteAddr;
302 endaddress = WriteAddr + NumHalfwordToWrite - 1;
303 lastloadedaddress = WriteAddr;
304
305 /*!< Issue unlock command sequence */
306 NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA);
307
308 NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
309
310 /*!< Write Write Buffer Load Command */
311 NOR_WRITE(ADDR_SHIFT(WriteAddr), 0x0025);
312 NOR_WRITE(ADDR_SHIFT(WriteAddr), (NumHalfwordToWrite - 1));
313
314 /*!< Load Data into NOR Buffer */
315 while(currentaddress <= endaddress)
316 {
317 /*!< Store last loaded address & data value (for polling) */
318 lastloadedaddress = currentaddress;
319
320 NOR_WRITE(ADDR_SHIFT(currentaddress), *pBuffer++);
321 currentaddress += 1;
322 }
323
324 NOR_WRITE(ADDR_SHIFT(lastloadedaddress), 0x29);
325
326 return(NOR_GetStatus(Program_Timeout));
327 }
328
329 /**
330 * @brief Reads a half-word from the NOR memory.
331 * @param ReadAddr: NOR memory internal address to read from.
332 * @retval Half-word read from the NOR memory
333 */
334 uint16_t NOR_ReadHalfWord(uint32_t ReadAddr)
335 {
336 NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA);
337 NOR_WRITE(ADDR_SHIFT(0x002AA), 0x0055);
338 NOR_WRITE((Bank1_NOR2_ADDR + ReadAddr), 0x00F0 );
339
340 return (*(__IO uint16_t *)((Bank1_NOR2_ADDR + ReadAddr)));
341 }
342
343 /**
344 * @brief Reads a block of data from the FSMC NOR memory.
345 * @param pBuffer: pointer to the buffer that receives the data read from the
346 * NOR memory.
347 * @param ReadAddr: NOR memory internal address to read from.
348 * @param NumHalfwordToRead : number of Half word to read.
349 * @retval None
350 */
351 void NOR_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
352 {
353 NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
354 NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
355 NOR_WRITE((Bank1_NOR2_ADDR + ReadAddr), 0x00F0);
356
357 for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /*!< while there is data to read */
358 {
359 /*!< Read a Halfword from the NOR */
360 *pBuffer++ = *(__IO uint16_t *)((Bank1_NOR2_ADDR + ReadAddr));
361 ReadAddr = ReadAddr + 2;
362 }
363 }
364
365 /**
366 * @brief Returns the NOR memory to Read mode.
367 * @param None
368 * @retval NOR_SUCCESS
369 */
370 NOR_Status NOR_ReturnToReadMode(void)
371 {
372 NOR_WRITE(Bank1_NOR2_ADDR, 0x00F0);
373
374 return (NOR_SUCCESS);
375 }
376
377 /**
378 * @brief Returns the NOR memory to Read mode and resets the errors in the NOR
379 * memory Status Register.
380 * @param None
381 * @retval NOR_SUCCESS
382 */
383 NOR_Status NOR_Reset(void)
384 {
385 NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA);
386 NOR_WRITE(ADDR_SHIFT(0x002AA), 0x0055);
387 NOR_WRITE(Bank1_NOR2_ADDR, 0x00F0);
388
389 return (NOR_SUCCESS);
390 }
391
392 /**
393 * @brief Returns the NOR operation status.
394 * @param Timeout: NOR progamming Timeout
395 * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
396 * or NOR_TIMEOUT
397 */
398 NOR_Status NOR_GetStatus(uint32_t Timeout)
399 {
400 uint16_t val1 = 0x00, val2 = 0x00;
401 NOR_Status status = NOR_ONGOING;
402 uint32_t timeout = Timeout;
403
404 /*!< Poll on NOR memory Ready/Busy signal ----------------------------------*/
405 while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6) != RESET) && (timeout > 0))
406 {
407 timeout--;
408 }
409
410 timeout = Timeout;
411
412 while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6) == RESET) && (timeout > 0))
413 {
414 timeout--;
415 }
416
417 /*!< Get the NOR memory operation status -----------------------------------*/
418 while((Timeout != 0x00) && (status != NOR_SUCCESS))
419 {
420 Timeout--;
421
422 /*!< Read DQ6 and DQ5 */
423 val1 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
424 val2 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
425
426 /*!< If DQ6 did not toggle between the two reads then return NOR_Success */
427 if((val1 & 0x0040) == (val2 & 0x0040))
428 {
429 return NOR_SUCCESS;
430 }
431
432 if((val1 & 0x0020) != 0x0020)
433 {
434 status = NOR_ONGOING;
435 }
436
437 val1 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
438 val2 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
439
440 if((val1 & 0x0040) == (val2 & 0x0040))
441 {
442 return NOR_SUCCESS;
443 }
444 else if((val1 & 0x0020) == 0x0020)
445 {
446 return NOR_ERROR;
447 }
448 }
449
450 if(Timeout == 0x00)
451 {
452 status = NOR_TIMEOUT;
453 }
454
455 /*!< Return the operation status */
456 return (status);
457 }
458
459 /**
460 * @}
461 */
462
463 /**
464 * @}
465 */
466
467 /**
468 * @}
469 */
470
471 /**
472 * @}
473 */
474
475 /**
476 * @}
477 */
478
479 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/