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comparison libs/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_onenand.h @ 0:c59513fd84fb

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Initial commit of STM32 test code.
author Daniel O'Connor <darius@dons.net.au>
date Mon, 03 Oct 2011 21:19:15 +1030
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1 /**
2 ******************************************************************************
3 * @file stm32100e_eval_fsmc_onenand.h
4 * @author MCD Application Team
5 * @version V4.5.0
6 * @date 07-March-2011
7 * @brief This file contains all the functions prototypes for the
8 * stm32100e_eval_fsmc_onenand firmware driver.
9 ******************************************************************************
10 * @attention
11 *
12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 *
19 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
20 ******************************************************************************
21 */
22
23 /* Define to prevent recursive inclusion -------------------------------------*/
24 #ifndef __STM32100E_EVAL_FSMC_ONENAND_H
25 #define __STM32100E_EVAL_FSMC_ONENAND_H
26
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30
31 /* Includes ------------------------------------------------------------------*/
32 #include "stm32f10x.h"
33
34 /** @addtogroup Utilities
35 * @{
36 */
37
38 /** @addtogroup STM32_EVAL
39 * @{
40 */
41
42 /** @addtogroup STM32100E_EVAL
43 * @{
44 */
45
46 /** @addtogroup STM32100E_EVAL_FSMC_ONENAND
47 * @{
48 */
49
50 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Exported_Types
51 * @{
52 */
53 typedef struct
54 {
55 uint16_t Manufacturer_ID;
56 uint16_t Device_ID;
57 }OneNAND_IDTypeDef;
58
59 /* OneNand Status */
60 typedef enum
61 {
62 OneNAND_SUCCESS = 0,
63 OneNAND_ONGOING,
64 OneNAND_ERROR,
65 OneNAND_TIMEOUT
66 }OneNAND_Status;
67
68 typedef struct
69 {
70 uint16_t Block;
71 uint16_t Page;
72 } OneNAND_ADDRESS;
73 /**
74 * @}
75 */
76
77 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Exported_Constants
78 * @{
79 */
80 /**
81 * @brief OneNAND memory command
82 */
83 #define OneNAND_CMD_ERASE ((uint16_t)0x0094)
84 #define OneNAND_CMD_PROGRAM ((uint16_t)0x0080)
85 #define OneNAND_CMD_RESET ((uint16_t)0x00F0)
86 #define OneNAND_CMD_READ_ID ((uint16_t)0x0090)
87 #define OneNAND_CMD_UNLOCK ((uint16_t)0x0023)
88 #define OneNAND_CMD_LOAD ((uint16_t)0x0000)
89
90 /**
91 * @brief OneNand Register description
92 */
93 #define OneNAND_REG_MANUFACTERID ((uint32_t)0x1E000) /* Manufacturer identification */
94 #define OneNAND_REG_DEVICEID ((uint32_t)0x1E002) /* Device identification */
95 #define OneNAND_REG_DATABUFFERSIZE ((uint32_t)0x1E006) /* Data Buffer size */
96 #define OneNAND_REG_BOOTBUFFERSIZE ((uint32_t)0x1E008) /* Boot Buffer size */
97 #define OneNAND_REG_AMOUNTOFBUFFERS ((uint32_t)0x1E00A) /* Amount of data/boot buffers */
98 #define OneNAND_REG_TECHNOLOGY ((uint32_t)0x1E00C) /* Info about technology */
99 #define OneNAND_REG_STARTADDRESS1 ((uint32_t)0x1E200) /* Nand Flash Block Address */
100 #define OneNAND_REG_STARTADDRESS3 ((uint32_t)0x1E204) /* Destination Block address for copy back program */
101 #define OneNAND_REG_STARTADDRESS4 ((uint32_t)0x1E206) /* Destination Page & sector address for copy back program */
102 #define OneNAND_REG_STARTADDRESINT8_T ((uint32_t)0x1E20E) /* Nand Flash Page & sector address */
103 #define OneNAND_REG_STARTBUFFER ((uint32_t)0x1E400) /* The meaning is with which buffer to start and how many
104 buffers to use for the data transfer */
105 #define OneNAND_REG_COMMAND ((uint32_t)0x1E440) /* Host control and memory operation commands*/
106 #define OneNAND_REG_SYSTEMCONFIGURATION ((uint32_t)0x1E442) /* Memory and host interface configuration */
107 #define OneNAND_REG_CONTROLSTATUS ((uint32_t)0x1E480) /* Control status and result of memory operation */
108 #define OneNAND_REG_INTERRUPT ((uint32_t)0x1E482) /* Memory Command Completion Interrupt Status */
109 #define OneNAND_REG_STARTBLOCKADDRESS ((uint32_t)0x1E498) /* Start memory block address in Write Protection mode */
110 #define OneNAND_REG_WRITEPROTECTIONSTATUS ((uint32_t)0x1E49C) /* Current memory Write Protection status */
111
112 /**
113 * @brief OneNand Memory partition description
114 */
115 #define OneNAND_DATA_RAM_0_0_ADD ((uint32_t)0x0400) /* DataRAM Main page0/sector0 */
116 #define OneNAND_DATA_RAM_0_0_REG ((uint32_t)0x0800) /* DataRAM 0_0 is selected with 4 sector */
117
118 #define OneNAND_DATA_RAM_0_1_ADD ((uint32_t)0x0600) /* DataRAM Main page0/sector1 */
119 #define OneNAND_DATA_RAM_0_1_REG ((uint32_t)0x0900) /* DataRAM 0_1 is selected with 4 sector */
120
121 #define OneNAND_DATA_RAM_0_2_ADD ((uint32_t)0x0800) /* DataRAM Main page0/sector2 */
122 #define OneNAND_DATA_RAM_0_2_REG ((uint32_t)0x0A00) /* DataRAM 0_2 is selected with 4 sector */
123
124 #define OneNAND_DATA_RAM_0_3_ADD ((uint32_t)0x0A00) /* DataRAM Main page0/sector3 */
125 #define OneNAND_DATA_RAM_0_3_REG ((uint32_t)0x0B00) /* DataRAM 0_3 is selected with 4 sector */
126
127 #define OneNAND_DATA_RAM_1_0_ADD ((uint32_t)0x0C00) /* DataRAM Main page1/sector0 */
128 #define OneNAND_DATA_RAM_1_0_REG ((uint32_t)0x0C00) /* DataRAM 1_0 is selected with 4 sector */
129
130 #define OneNAND_DATA_RAM_1_1_ADD ((uint32_t)0x0E00) /* DataRAM Main page1/sector1 */
131 #define OneNAND_DATA_RAM_1_1_REG ((uint32_t)0x0D00) /* DataRAM 1_1 is selected with 4 sector */
132
133 #define OneNAND_DATA_RAM_1_2_ADD ((uint32_t)0x1000) /* DataRAM Main page1/sector2 */
134 #define OneNAND_DATA_RAM_1_2_REG ((uint32_t)0x0E00) /* DataRAM 1_2 is selected with 4 sector */
135
136 #define OneNAND_DATA_RAM_1_3_ADD ((uint32_t)0x1200) /* DataRAM Main page1/sector3 */
137 #define OneNAND_DATA_RAM_1_3_REG ((uint32_t)0x0F00) /* DataRAM 1_3 is selected with 4 sector */
138
139 /**
140 * @}
141 */
142
143 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Exported_Macros
144 * @{
145 */
146 /**
147 * @}
148 */
149
150 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Exported_Functions
151 * @{
152 */
153 void OneNAND_Init(void);
154 void OneNAND_Reset(void);
155 void OneNAND_ReadID(OneNAND_IDTypeDef* OneNAND_ID);
156 uint16_t OneNAND_UnlockBlock(uint32_t BlockNumber);
157 uint16_t OneNAND_EraseBlock(uint32_t BlockNumber);
158 uint16_t OneNAND_WriteBuffer(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToWrite);
159 void OneNAND_AsynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead);
160 void OneNAND_SynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead);
161 uint16_t OneNAND_ReadStatus(void);
162 uint16_t OneNAND_ReadControllerStatus(void);
163
164 #ifdef __cplusplus
165 }
166 #endif
167
168 #endif /* __STM32100E_EVAL_FSMC_ONENAND_H */
169 /**
170 * @}
171 */
172
173 /**
174 * @}
175 */
176
177 /**
178 * @}
179 */
180
181 /**
182 * @}
183 */
184
185 /**
186 * @}
187 */
188
189 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/