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Initial commit of STM32 test code.
author Daniel O'Connor <darius@dons.net.au>
date Mon, 03 Oct 2011 21:19:15 +1030
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1 /**
2 ******************************************************************************
3 * @file stm32100e_eval_fsmc_onenand.c
4 * @author MCD Application Team
5 * @version V4.5.0
6 * @date 07-March-2011
7 * @brief This file provides a set of functions needed to drive the
8 * KFG1216U2A/B-DIB6 OneNAND memory mounted on STM32100E-EVAL board.
9 ******************************************************************************
10 * @attention
11 *
12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 *
19 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
20 ******************************************************************************
21 */
22
23 /* Includes ------------------------------------------------------------------*/
24 #include "stm32100e_eval_fsmc_onenand.h"
25
26 /** @addtogroup Utilities
27 * @{
28 */
29
30 /** @addtogroup STM32_EVAL
31 * @{
32 */
33
34 /** @addtogroup STM32100E_EVAL
35 * @{
36 */
37
38 /** @addtogroup STM32100E_EVAL_FSMC_ONENAND
39 * @brief This file provides a set of functions needed to drive the
40 * KFG1216x2A-xxB5 OneNAND memory mounted on STM32100E-EVAL board.
41 * @{
42 */
43
44 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Types
45 * @{
46 */
47 /**
48 * @}
49 */
50
51
52 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Defines
53 * @{
54 */
55 #define BANK1_ONENAND1_ADDR ((uint32_t)0x60000000)
56 #define ONENAND_BOOTPARTITION_ADDR ((uint32_t)BANK1_ONENAND1_ADDR)
57
58
59 /**
60 * @}
61 */
62
63 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Macros
64 * @{
65 */
66 #define OneNAND_WRITE(Address, Data) (*(__IO uint16_t *)(Address) = (Data))
67
68 /**
69 * @}
70 */
71
72
73 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Variables
74 * @{
75 */
76 /**
77 * @}
78 */
79
80
81 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Function_Prototypes
82 * @{
83 */
84 /**
85 * @}
86 */
87
88
89 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Functions
90 * @{
91 */
92
93 /**
94 * @brief Configures the FSMC and GPIOs to interface with the OneNAND memory.
95 * This function must be called before any write/read operation on the
96 * OneNAND.
97 * @param None
98 * @retval None
99 */
100 void OneNAND_Init(void)
101 {
102 FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
103 FSMC_NORSRAMTimingInitTypeDef p;
104 GPIO_InitTypeDef GPIO_InitStructure;
105
106
107 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
108
109 /*-- GPIO Configuration ------------------------------------------------------*/
110 /* OneNAND Data lines configuration */
111 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE |
112 RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE);
113
114 /*-- GPIO Configuration ------------------------------------------------------*/
115 /*!< OneNAND Data lines configuration */
116 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
117 GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
118 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
119 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
120 GPIO_Init(GPIOD, &GPIO_InitStructure);
121
122 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
123 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
124 GPIO_Pin_15;
125 GPIO_Init(GPIOE, &GPIO_InitStructure);
126
127 /*!< OneNAND Address lines configuration */
128 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
129 GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
130 GPIO_Pin_14 | GPIO_Pin_15;
131 GPIO_Init(GPIOF, &GPIO_InitStructure);
132
133 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
134 GPIO_Pin_4 | GPIO_Pin_5;
135 GPIO_Init(GPIOG, &GPIO_InitStructure);
136
137 /*!< CLK, NOE and NWE configuration */
138 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 |GPIO_Pin_5;
139 GPIO_Init(GPIOD, &GPIO_InitStructure);
140
141 /*!< NE1 configuration */
142 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
143 GPIO_Init(GPIOD, &GPIO_InitStructure);
144
145 /*!< NL configuration */
146 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
147 GPIO_Init(GPIOB, &GPIO_InitStructure);
148 GPIO_PinRemapConfig(GPIO_Remap_FSMC_NADV, DISABLE);
149
150 /*!< NWAIT configuration */
151 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
152 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
153 GPIO_Init(GPIOD, &GPIO_InitStructure);
154
155 /*-- FSMC Configuration ----------------------------------------------------*/
156 p.FSMC_AddressSetupTime = 0x01;
157 p.FSMC_AddressHoldTime = 0x00;
158 p.FSMC_DataSetupTime = 0x05;
159 p.FSMC_BusTurnAroundDuration = 0x02;
160 p.FSMC_CLKDivision = 0x1;
161 p.FSMC_DataLatency = 0x01;
162 p.FSMC_AccessMode = FSMC_AccessMode_B;
163
164 FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM1;
165 FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
166 FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR;
167 FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
168 FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Enable;
169 FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
170 FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
171 FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
172 FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
173 FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
174 FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Enable;
175 FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
176 FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
177 FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
178 FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
179
180 FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
181 FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE);
182 }
183
184 /**
185 * @brief Resets the OneNAND memory.
186 * @param None
187 * @retval None
188 */
189 void OneNAND_Reset(void)
190 {
191 OneNAND_WRITE(ONENAND_BOOTPARTITION_ADDR, OneNAND_CMD_RESET);
192 }
193
194 /**
195 * @brief Reads OneNAND memory's Manufacturer and Device Code.
196 * @param OneNAND_ID: pointer to a OneNAND_IDTypeDef structure which will hold
197 * the Manufacturer and Device Code.
198 * @retval None
199 */
200 void OneNAND_ReadID(OneNAND_IDTypeDef* OneNAND_ID)
201 {
202 uint16_t status = 0x0;
203
204 /* Wait till no ongoing operation */
205 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
206
207 while((status & 0x8000) == 0x8000)
208 {
209 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
210 }
211
212 /* Read ID data */
213 OneNAND_ID->Manufacturer_ID = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_MANUFACTERID);
214 OneNAND_ID->Device_ID = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_DEVICEID);
215
216 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION) = 0x40E0;
217 }
218
219 /**
220 * @brief Unlocks the specified OneNAND memory block (128Kb).
221 * @param BlockNumber: specifies the block number to be erased. This parameter
222 * should be between 0 and 511.
223 * @retval OneNAND memory Interrupt Status.
224 */
225 uint16_t OneNAND_UnlockBlock(uint32_t BlockNumber)
226 {
227 uint16_t status = 0;
228
229 /* Wait till no ongoing operation */
230 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
231
232 while((status & 0x8000) == 0x8000)
233 {
234 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
235 }
236
237 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBLOCKADDRESS) = BlockNumber;
238 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
239 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_UNLOCK;
240
241 /* Wait till the command is completed */
242 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
243
244 while((status & 0x8000) != 0x8000)
245 {
246 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
247 }
248
249 /* Get the Controller Status */
250 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
251
252 return (status);
253 }
254
255 /**
256 * @brief Erases the specified OneNAND memory block (128Kb).
257 * @param BlockNumber: specifies the block number to be erased. This parameter
258 * should be between 0 and 511.
259 * @retval OneNAND memory Interrupt Status.
260 */
261 uint16_t OneNAND_EraseBlock(uint32_t BlockNumber)
262 {
263 uint16_t status = 0x0;
264
265 /* Wait till no ongoing operation */
266 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
267
268 while((status & 0x8000) == 0x8000)
269 {
270 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
271 }
272
273 /* Erase operation */
274 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = BlockNumber;
275 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
276 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_ERASE;
277
278 /* Wait till no error is generated */
279 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
280
281 while((status & 0x0400) == 0x0400)
282 {
283 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
284 }
285
286 /* Wait till the command is completed */
287 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
288
289 while((status & 0x8000) != 0x8000)
290 {
291 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
292 }
293
294 /* Get the Controller Status */
295 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
296
297 return (status);
298 }
299
300 /**
301 * @brief Writes a Half-word buffer to the OneNAND memory.
302 * @param pBuffer: pointer to buffer.
303 * @param WriteAddr: OneNAND memory internal address from which the data will be
304 * written.
305 * @param NumHalfwordToWrite: number of half-words to write.
306 * @retval OneNAND memory Controller Status.
307 */
308 uint16_t OneNAND_WriteBuffer(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToWrite)
309 {
310 uint32_t datacounter = 0;
311 uint16_t status = 0;
312
313 /* Load the buffer to be written into the DATA RAM0*/
314 for(datacounter = 0; datacounter < NumHalfwordToWrite; datacounter++)
315 {
316 *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_0_0_ADD) + (2*datacounter)) = pBuffer[datacounter];
317 }
318
319 /* Write operation from DATA RAM0 to NAND address*/
320 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/
321 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2); /* NAND Flash start page address */
322 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_0_0_REG;/* BufferRAM Sector Count (BSC) and BufferRAM Sector Address (BSA).*/
323 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
324 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_PROGRAM; /* Command */
325
326 /* Wait till the command is completed */
327 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
328
329 while((status & 0x8000) != 0x8000)
330 {
331 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
332 }
333
334 /* Wait till the write interrupt is set */
335 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
336
337 while((status & 0x40) != 0x40)
338 {
339 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
340 }
341
342 /* Get the Controller Status */
343 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
344
345 return (status);
346 }
347
348 /**
349 * @brief Reads a block of data from the OneNAND memory using asynchronous mode.
350 * @param pBuffer: pointer to the buffer that receives the data read from the
351 * OneNAND memory.
352 * @param ReadAddr: OneNAND memory internal address to read from.
353 * @param NumHalfwordToRead: number of half-words to read.
354 * @retval None
355 */
356 void OneNAND_AsynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead)
357 {
358 uint16_t datatmp = 0x0, index = 0;
359 uint16_t status = 0;
360
361 datatmp = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION);
362
363 /* Set the asynchronous read mode */
364 OneNAND_WRITE(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION, (datatmp& 0x7FFF));
365
366 /* Load data from the read address to the DATA RAM 1 setor 1 */
367 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/
368 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2);
369 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_1_0_REG;
370 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
371 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_LOAD; /* Command */
372
373 /* Wait till the command is completed */
374 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
375
376 while((status & 0x8000) != 0x8000)
377 {
378 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
379 }
380
381 /* Read Controller status */
382 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
383
384 /* Read data */
385 for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /* While there is data to read */
386 {
387 /* Read a Halfword from the memory */
388 *pBuffer++ = *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_1_0_ADD)+ 2*index);
389 index++;
390 }
391 }
392
393 /**
394 * @brief Reads a block of data from the OneNAND memory using synchronous mode.
395 * @param pBuffer: pointer to the buffer that receives the data read from the
396 * OneNAND memory.
397 * @param ReadAddr: OneNAND memory internal address to read from.
398 * @param NumHalfwordToRead: number of half-words to read.
399 * @retval None
400 */
401 void OneNAND_SynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead)
402 {
403 uint16_t index = 0;
404 uint16_t status = 0;
405
406 /* Set the asynchronous read mode */
407 OneNAND_WRITE(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION, 0xB4C0);
408
409
410 /* Load data from the read address to the DATA RAM 1 setor 1 */
411 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/
412 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2);
413 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_1_0_REG;
414 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
415 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_LOAD; /* Command */
416
417 /* Wait till the command is completed */
418 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
419
420 while((status & 0x8000) != 0x8000)
421 {
422 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
423 }
424
425 /* Read Controller status */
426 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
427
428 /* Read data */
429 for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /* While there is data to read */
430 {
431 *pBuffer++ = *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_1_0_ADD + 2*index));
432 index++;
433 }
434 }
435
436 /**
437 * @brief Reads the OneNAND memory Interrupt status.
438 * @param None
439 * @retval OneNAND memory Interrupt Status.
440 */
441 uint16_t OneNAND_ReadStatus(void)
442 {
443 __IO uint16_t status = 0x0;
444
445 /* Read Status */
446 return (status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT));
447 }
448
449 /**
450 * @brief Reads the OneNAND Controller status.
451 * @param None
452 * @retval OneNAND Controller Status.
453 */
454 uint16_t OneNAND_ReadControllerStatus(void)
455 {
456 __IO uint16_t status = 0x0;
457
458 /* Read Controller Status */
459 return (status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS));
460 }
461
462 /**
463 * @}
464 */
465
466 /**
467 * @}
468 */
469
470 /**
471 * @}
472 */
473
474 /**
475 * @}
476 */
477
478 /**
479 * @}
480 */
481
482 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/