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Initial commit of STM32 test code.
author Daniel O'Connor <darius@dons.net.au>
date Mon, 03 Oct 2011 21:19:15 +1030
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1 /**
2 @page TIM_TimeBase TIM Time Base example
3
4 @verbatim
5 ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
6 * @file TIM/TimeBase/readme.txt
7 * @author MCD Application Team
8 * @version V3.5.0
9 * @date 08-April-2011
10 * @brief Description of the TIM Time Base example.
11 ******************************************************************************
12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 ******************************************************************************
19 @endverbatim
20
21 @par Example Description
22
23 This example shows how to configure the TIM peripheral in Output Compare Timing
24 mode with the corresponding Interrupt requests for each channel in order to generate
25 4 different time bases.
26
27 The TIM2CLK frequency is set to SystemCoreClock / 2 (Hz), to get TIM2 counter
28 clock at 6 MHz so the Prescaler is computed as following:
29 - Prescaler = (TIM2CLK / TIM2 counter clock) - 1
30 SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
31 and Connectivity line devices and to 24 MHz for Low-Density Value line,
32 Medium-Density Value line and High-Density devices.
33
34 The TIM2 CC1 register value is equal to 40961,
35 CC1 update rate = TIM2 counter clock / CCR1_Val = 146.48 Hz,
36 so the TIM2 Channel 1 generates an interrupt each 6.8ms
37
38 The TIM2 CC2 register is equal to 27309,
39 CC2 update rate = TIM2 counter clock / CCR2_Val = 219.7 Hz
40 so the TIM2 Channel 2 generates an interrupt each 4.55ms
41
42 The TIM2 CC3 register is equal to 13654,
43 CC3 update rate = TIM2 counter clock / CCR3_Val = 439.4Hz
44 so the TIM2 Channel 3 generates an interrupt each 2.27ms
45
46 The TIM2 CC4 register is equal to 6826,
47 CC4 update rate = TIM2 counter clock / CCR4_Val = 878.9 Hz
48 so the TIM2 Channel 4 generates an interrupt each 1.13ms.
49
50 When the counter value reaches the Output compare registers values, the Output
51 Compare interrupts are generated and, in the handler routine, 4 pins(PC.06, PC.07,
52 PC.08 and PC.09) are toggled with the following frequencies:
53
54 - PC.06: 73.24Hz (CC1)
55 - PC.07: 109.8Hz (CC2)
56 - PC.08: 219.7Hz (CC3)
57 - PC.09: 439.4Hz (CC4)
58
59 @par Directory contents
60
61 - TIM/TimeBase/stm32f10x_conf.h Library Configuration file
62 - TIM/TimeBase/stm32f10x_it.c Interrupt handlers
63 - TIM/TimeBase/stm32f10x_it.h Interrupt handlers header file
64 - TIM/TimeBase/main.c Main program
65 - TIM/TimeBase/system_stm32f10x.c STM32F10x system source file
66
67 @par Hardware and Software environment
68
69 - This example runs on STM32F10x Connectivity line, High-Density, High-Density
70 Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density
71 and Low-Density Value line Devices.
72
73 - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
74 Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line),
75 STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density)
76 evaluation boards and can be easily tailored to any other supported device
77 and development board.
78
79 - STM32100E-EVAL, STM3210E-EVAL, STM32100E-EVAL, STM3210B-EVAL and STM3210C-EVAL Set-up
80 - Connect an oscilloscope on PC.06, PC.07, PC.08 and PC.09 to show the
81 different Time Base signals.
82
83 @par How to use it ?
84
85 In order to make the program work, you must do the following :
86 - Copy all source files from this example folder to the template folder under
87 Project\STM32F10x_StdPeriph_Template
88 - Open your preferred toolchain
89 - Rebuild all files and load your image into target memory
90 - Run the example
91
92 @note
93 - Low-density Value line devices are STM32F100xx microcontrollers where the
94 Flash memory density ranges between 16 and 32 Kbytes.
95 - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
96 microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
97 - Medium-density Value line devices are STM32F100xx microcontrollers where
98 the Flash memory density ranges between 64 and 128 Kbytes.
99 - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
100 microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
101 - High-density Value line devices are STM32F100xx microcontrollers where
102 the Flash memory density ranges between 256 and 512 Kbytes.
103 - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
104 the Flash memory density ranges between 256 and 512 Kbytes.
105 - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
106 the Flash memory density ranges between 512 and 1024 Kbytes.
107 - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
108
109 * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
110 */