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Initial commit of STM32 test code.
author Daniel O'Connor <darius@dons.net.au>
date Mon, 03 Oct 2011 21:19:15 +1030
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1 /**
2 @page TIM_OCToggle TIM OC Toggle example
3
4 @verbatim
5 ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
6 * @file TIM/OCToggle/readme.txt
7 * @author MCD Application Team
8 * @version V3.5.0
9 * @date 08-April-2011
10 * @brief Description of the TIM OC Toggle example.
11 ******************************************************************************
12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 ******************************************************************************
19 @endverbatim
20
21 @par Example Description
22
23 This example shows how to configure the TIM3 peripheral to generate four different
24 signals with four different frequencies.
25
26 The TIM3CLK frequency is set to SystemCoreClock / 2 (Hz), and we want to get TIM3
27 counter clock at 12 MHz so the Prescaler is computed as following:
28 - Prescaler = (TIM3CLK / TIM3 counter clock) - 1
29 SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
30 and Connectivity line devices and to 24 MHz for Low-Density Value line,
31 Medium-Density Value line and High-Density devices.
32
33 The TIM3 CCR1 register value is equal to 32768:
34 CC1 update rate = TIM3 counter clock / CCR1_Val = 366.2 Hz,
35 so the TIM3 Channel 1 generates a periodic signal with a frequency equal to 183.1 Hz.
36
37 The TIM3 CCR2 register is equal to 16384:
38 CC2 update rate = TIM3 counter clock / CCR2_Val = 732.4 Hz
39 so the TIM3 channel 2 generates a periodic signal with a frequency equal to 366.3 Hz.
40
41 The TIM3 CCR3 register is equal to 8192:
42 CC3 update rate = TIM3 counter clock / CCR3_Val = 1464.8 Hz
43 so the TIM3 channel 3 generates a periodic signal with a frequency equal to 732.4 Hz.
44
45 The TIM3 CCR4 register is equal to 4096:
46 CC4 update rate = TIM3 counter clock / CCR4_Val = 2929.6 Hz
47 so the TIM3 channel 4 generates a periodic signal with a frequency equal to 1464.8 Hz.
48
49 @par Directory contents
50
51 - TIM/OCToggle/stm32f10x_conf.h Library Configuration file
52 - TIM/OCToggle/stm32f10x_it.c Interrupt handlers
53 - TIM/OCToggle/stm32f10x_it.h Interrupt handlers header file
54 - TIM/OCToggle/main.c Main program
55 - TIM/OCToggle/system_stm32f10x.c STM32F10x system source file
56
57 @par Hardware and Software environment
58
59 - This example runs on STM32F10x Connectivity line, High-Density, High-Density
60 Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density
61 and Low-Density Value line Devices.
62
63 - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
64 Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line),
65 STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density)
66 evaluation boards and can be easily tailored to any other supported device
67 and development board.
68
69
70 - STM3210C-EVAL Set-up
71 - Connect the TIM1 pins(TIM3 full remapped pins) to an oscilloscope to monitor
72 the different waveforms:
73 - PC.06 (TIM3_CH1)
74 - PC.07 (TIM3_CH2)
75 - PC.08 (TIM3_CH3)
76 - PC.09 (TIM3_CH4)
77
78 - STM32100B-EVAL, STM3210E-EVAL, STM32100E-EVAL and STM3210B-EVAL Set-up
79 - Connect the following pins to an oscilloscope to monitor the different
80 waveforms:
81 - PA.06 (TIM3_CH1)
82 - PA.07 (TIM3_CH2)
83 - PB.00 (TIM3_CH3)
84 - PB.01 (TIM3_CH4)
85
86 @par How to use it ?
87
88 In order to make the program work, you must do the following :
89 - Copy all source files from this example folder to the template folder under
90 Project\STM32F10x_StdPeriph_Template
91 - Open your preferred toolchain
92 - Rebuild all files and load your image into target memory
93 - Run the example
94
95 @note
96 - Low-density Value line devices are STM32F100xx microcontrollers where the
97 Flash memory density ranges between 16 and 32 Kbytes.
98 - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
99 microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
100 - Medium-density Value line devices are STM32F100xx microcontrollers where
101 the Flash memory density ranges between 64 and 128 Kbytes.
102 - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
103 microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
104 - High-density Value line devices are STM32F100xx microcontrollers where
105 the Flash memory density ranges between 256 and 512 Kbytes.
106 - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
107 the Flash memory density ranges between 256 and 512 Kbytes.
108 - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
109 the Flash memory density ranges between 512 and 1024 Kbytes.
110 - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
111
112 * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
113 */