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Initial commit of STM32 test code.
author Daniel O'Connor <darius@dons.net.au>
date Mon, 03 Oct 2011 21:19:15 +1030
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1 /**
2 @page TIM_OCInactive TIM OC Inactive example
3
4 @verbatim
5 ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
6 * @file TIM/OCInactive/readme.txt
7 * @author MCD Application Team
8 * @version V3.5.0
9 * @date 08-April-2011
10 * @brief Description of the TIM OC Inactive example.
11 ******************************************************************************
12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 ******************************************************************************
19 @endverbatim
20
21 @par Example Description
22
23 This example shows how to configure the TIM peripheral in Output Compare Inactive
24 mode with the corresponding Interrupt requests for each channel.
25
26 The TIM2CLK frequency is set to SystemCoreClock / 2 (Hz), and the objective is
27 to get TIM2 counter clock at 1 KHz so the Prescaler is computed as following:
28 - Prescaler = (TIM2CLK / TIM2 counter clock) - 1
29 SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
30 and Connectivity line devices and to 24 MHz for Value line devices.
31
32 The TIM2 CCR1 register value is equal to 1000:
33 TIM2_CC1 delay = CCR1_Val/TIM2 counter clock = 1000 ms
34 so the PC.06 is reset after a delay equal to 1000 ms.
35
36 The TIM2 CCR2 register value is equal to 500:
37 TIM2_CC2 delay = CCR2_Val/TIM2 counter clock = 500 ms
38 so the PC.07 is reset after a delay equal to 500 ms.
39
40 The TIM2 CCR3 register value is equal to 250:
41 TIM2_CC3 delay = CCR3_Val/TIM2 counter clock = 250 ms
42 so the PC.08 is reset after a delay equal to 250 ms.
43
44 The TIM2 CCR4 register value is equal to 125:
45 TIM2_CC4 delay = CCR4_Val/TIM2 counter clock = 125 ms
46 so the PC.09 is reset after a delay equal to 125 ms.
47
48 While the counter is lower than the Output compare registers values, which
49 determines the Output delay, the PC.06, PC.07, PC.08 and PC.09 pin are turned on.
50
51 When the counter value reaches the Output compare registers values, the Output
52 Compare interrupts are generated and, in the handler routine, these pins are turned off.
53
54 @par Directory contents
55
56 - TIM/OCInactive/stm32f10x_conf.h Library Configuration file
57 - TIM/OCInactive/stm32f10x_it.c Interrupt handlers
58 - TIM/OCInactive/stm32f10x_it.h Interrupt handlers header file
59 - TIM/OCInactive/main.c Main program
60 - TIM/OCInactive/system_stm32f10x.c STM32F10x system source file
61
62 @par Hardware and Software environment
63
64 - This example runs on STM32F10x Connectivity line, High-Density, High-Density
65 Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density
66 and Low-Density Value line Devices.
67
68 - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
69 Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line),
70 STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density)
71 evaluation boards and can be easily tailored to any other supported device
72 and development board.
73
74 - STM32100B-EVAL, STM3210E-EVAL, STM32100E-EVAL STM3210B-EVAL and STM3210C-EVAL Set-up
75 - Connect the following pins to an oscilloscope to monitor the different
76 waveforms:
77 - PC.06
78 - PC.07
79 - PC.08
80 - PC.09
81
82 @par How to use it ?
83
84 In order to make the program work, you must do the following :
85 - Copy all source files from this example folder to the template folder under
86 Project\STM32F10x_StdPeriph_Template
87 - Open your preferred toolchain
88 - Rebuild all files and load your image into target memory
89 - Run the example
90
91 @note
92 - Low-density Value line devices are STM32F100xx microcontrollers where the
93 Flash memory density ranges between 16 and 32 Kbytes.
94 - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
95 microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
96 - Medium-density Value line devices are STM32F100xx microcontrollers where
97 the Flash memory density ranges between 64 and 128 Kbytes.
98 - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
99 microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
100 - High-density Value line devices are STM32F100xx microcontrollers where
101 the Flash memory density ranges between 256 and 512 Kbytes.
102 - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
103 the Flash memory density ranges between 256 and 512 Kbytes.
104 - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
105 the Flash memory density ranges between 512 and 1024 Kbytes.
106 - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
107
108 * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
109 */