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comparison libs/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/main.c @ 0:c59513fd84fb

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Initial commit of STM32 test code.
author Daniel O'Connor <darius@dons.net.au>
date Mon, 03 Oct 2011 21:19:15 +1030
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1 /**
2 ******************************************************************************
3 * @file TIM/DMA/main.c
4 * @author MCD Application Team
5 * @version V3.5.0
6 * @date 08-April-2011
7 * @brief Main program body
8 ******************************************************************************
9 * @attention
10 *
11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 *
18 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
19 ******************************************************************************
20 */
21
22 /* Includes ------------------------------------------------------------------*/
23 #include "stm32f10x.h"
24
25 /** @addtogroup STM32F10x_StdPeriph_Examples
26 * @{
27 */
28
29 /** @addtogroup TIM_DMA
30 * @{
31 */
32
33 /* Private typedef -----------------------------------------------------------*/
34 /* Private define ------------------------------------------------------------*/
35 #define TIM1_CCR3_Address 0x40012C3C
36
37 /* Private macro -------------------------------------------------------------*/
38 /* Private variables ---------------------------------------------------------*/
39 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
40 TIM_OCInitTypeDef TIM_OCInitStructure;
41 uint16_t SRC_Buffer[3] = {0, 0, 0};
42 uint16_t TimerPeriod = 0;
43
44 /* Private function prototypes -----------------------------------------------*/
45 void RCC_Configuration(void);
46 void GPIO_Configuration(void);
47 void DMA_Configuration(void);
48
49 /* Private functions ---------------------------------------------------------*/
50
51 /**
52 * @brief Main program
53 * @param None
54 * @retval None
55 */
56 int main(void)
57 {
58 /*!< At this stage the microcontroller clock setting is already configured,
59 this is done through SystemInit() function which is called from startup
60 file (startup_stm32f10x_xx.s) before to branch to application main.
61 To reconfigure the default setting of SystemInit() function, refer to
62 system_stm32f10x.c file
63 */
64
65 /* System Clocks Configuration */
66 RCC_Configuration();
67
68 /* GPIO Configuration */
69 GPIO_Configuration();
70
71 /* DMA Configuration */
72 DMA_Configuration();
73
74 /* TIM1 DMA Transfer example -------------------------------------------------
75 TIM1CLK = SystemCoreClock, Prescaler = 0, TIM1 counter clock = SystemCoreClock
76 SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
77 and Connectivity line devices and to 24 MHz for Low-Density Value line and
78 Medium-Density Value line devices.
79
80 The objective is to configure TIM1 channel 3 to generate complementary PWM
81 signal with a frequency equal to 17.57 KHz:
82 - TIM1_Period = (SystemCoreClock / 17570) - 1
83 and a variable duty cycle that is changed by the DMA after a specific number of
84 Update DMA request.
85
86 The number of this repetitive requests is defined by the TIM1 Repetition counter,
87 each 3 Update Requests, the TIM1 Channel 3 Duty Cycle changes to the next new
88 value defined by the SRC_Buffer .
89 -----------------------------------------------------------------------------*/
90 /* Compute the value to be set in ARR register to generate signal frequency at 17.57 Khz */
91 TimerPeriod = (SystemCoreClock / 17570 ) - 1;
92 /* Compute CCR1 value to generate a duty cycle at 50% */
93 SRC_Buffer[0] = (uint16_t) (((uint32_t) 5 * (TimerPeriod - 1)) / 10);
94 /* Compute CCR1 value to generate a duty cycle at 37.5% */
95 SRC_Buffer[1] = (uint16_t) (((uint32_t) 375 * (TimerPeriod - 1)) / 1000);
96 /* Compute CCR1 value to generate a duty cycle at 25% */
97 SRC_Buffer[2] = (uint16_t) (((uint32_t) 25 * (TimerPeriod - 1)) / 100);
98
99 /* TIM1 Peripheral Configuration --------------------------------------------*/
100 /* Time Base configuration */
101 TIM_TimeBaseStructure.TIM_Prescaler = 0;
102 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
103 TIM_TimeBaseStructure.TIM_Period = TimerPeriod;
104 TIM_TimeBaseStructure.TIM_ClockDivision = 0;
105 TIM_TimeBaseStructure.TIM_RepetitionCounter = 2;
106
107 TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
108
109 /* Channel 3 Configuration in PWM mode */
110 TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
111 TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
112 TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
113 TIM_OCInitStructure.TIM_Pulse = SRC_Buffer[0];
114 TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
115 TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low;
116 TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
117 TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
118
119 TIM_OC3Init(TIM1, &TIM_OCInitStructure);
120
121 /* TIM1 Update DMA Request enable */
122 TIM_DMACmd(TIM1, TIM_DMA_Update, ENABLE);
123
124 /* TIM1 counter enable */
125 TIM_Cmd(TIM1, ENABLE);
126
127 /* Main Output Enable */
128 TIM_CtrlPWMOutputs(TIM1, ENABLE);
129
130 while (1)
131 {}
132 }
133
134 /**
135 * @brief Configures the different system clocks.
136 * @param None
137 * @retval None
138 */
139 void RCC_Configuration(void)
140 {
141 /* TIM1, GPIOA and GPIOB clock enable */
142 RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA |
143 RCC_APB2Periph_GPIOB, ENABLE);
144 /* DMA clock enable */
145 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
146 }
147
148 /**
149 * @brief Configure the TIM1 Pins.
150 * @param None
151 * @retval None
152 */
153 void GPIO_Configuration(void)
154 {
155 GPIO_InitTypeDef GPIO_InitStructure;
156
157 /* GPIOA Configuration: Channel 3 as alternate function push-pull */
158 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
159 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
160 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
161 GPIO_Init(GPIOA, &GPIO_InitStructure);
162
163 /* GPIOB Configuration: Channel 3N as alternate function push-pull */
164 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
165 GPIO_Init(GPIOB, &GPIO_InitStructure);
166 }
167
168 /**
169 * @brief Configures the DMA.
170 * @param None
171 * @retval None
172 */
173 void DMA_Configuration(void)
174 {
175 DMA_InitTypeDef DMA_InitStructure;
176
177 /* DMA1 Channel5 Config */
178 DMA_DeInit(DMA1_Channel5);
179
180 DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)TIM1_CCR3_Address;
181 DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SRC_Buffer;
182 DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
183 DMA_InitStructure.DMA_BufferSize = 3;
184 DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
185 DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
186 DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
187 DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
188 DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
189 DMA_InitStructure.DMA_Priority = DMA_Priority_High;
190 DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
191
192 DMA_Init(DMA1_Channel5, &DMA_InitStructure);
193
194 /* DMA1 Channel5 enable */
195 DMA_Cmd(DMA1_Channel5, ENABLE);
196 }
197
198 #ifdef USE_FULL_ASSERT
199
200 /**
201 * @brief Reports the name of the source file and the source line number
202 * where the assert_param error has occurred.
203 * @param file: pointer to the source file name
204 * @param line: assert_param error line source number
205 * @retval None
206 */
207 void assert_failed(uint8_t* file, uint32_t line)
208 {
209 /* User can add his own implementation to report the file name and line number,
210 ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
211
212 while (1)
213 {}
214 }
215
216 #endif
217
218 /**
219 * @}
220 */
221
222 /**
223 * @}
224 */
225
226 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/