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comparison libs/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c @ 0:c59513fd84fb

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Initial commit of STM32 test code.
author Daniel O'Connor <darius@dons.net.au>
date Mon, 03 Oct 2011 21:19:15 +1030
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1 /**
2 ******************************************************************************
3 * @file RCC/RCC_ClockConfig/stm32f10x_it.c
4 * @author MCD Application Team
5 * @version V3.5.0
6 * @date 08-April-2011
7 * @brief Main Interrupt Service Routines.
8 * This file provides template for all exceptions handler and peripherals
9 * interrupt service routine.
10 ******************************************************************************
11 * @attention
12 *
13 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
14 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
15 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
16 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
17 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
18 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
19 *
20 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
21 ******************************************************************************
22 */
23
24 /* Includes ------------------------------------------------------------------*/
25 #include "stm32f10x_it.h"
26 #include "main.h"
27
28 /** @addtogroup STM32F10x_StdPeriph_Examples
29 * @{
30 */
31
32 /** @addtogroup RCC_ClockConfig
33 * @{
34 */
35
36 /* Private typedef -----------------------------------------------------------*/
37 /* Private define ------------------------------------------------------------*/
38 /* Private macro -------------------------------------------------------------*/
39 /* Private variables ---------------------------------------------------------*/
40 /* Private function prototypes -----------------------------------------------*/
41 /* Private functions ---------------------------------------------------------*/
42
43 /******************************************************************************/
44 /* Cortex-M3 Processor Exceptions Handlers */
45 /******************************************************************************/
46
47 /**
48 * @brief This function handles NMI exception.
49 * @param None
50 * @retval None
51 */
52 void NMI_Handler(void)
53 {
54 /* This interrupt is generated when HSE clock fails */
55
56 if (RCC_GetITStatus(RCC_IT_CSS) != RESET)
57 {/* At this stage: HSE, PLL are disabled (but no change on PLL config) and HSI
58 is selected as system clock source */
59
60 /* Enable HSE */
61 RCC_HSEConfig(RCC_HSE_ON);
62
63 /* Enable HSE Ready interrupt */
64 RCC_ITConfig(RCC_IT_HSERDY, ENABLE);
65
66 #ifndef SYSCLK_HSE
67 #ifdef STM32F10X_CL
68 /* Enable PLL and PLL2 Ready interrupts */
69 RCC_ITConfig(RCC_IT_PLLRDY | RCC_IT_PLL2RDY, ENABLE);
70 #else
71 /* Enable PLL Ready interrupt */
72 RCC_ITConfig(RCC_IT_PLLRDY, ENABLE);
73 #endif /* STM32F10X_CL */
74 #endif /* SYSCLK_HSE */
75
76 /* Clear Clock Security System interrupt pending bit */
77 RCC_ClearITPendingBit(RCC_IT_CSS);
78
79 /* Once HSE clock recover, the HSERDY interrupt is generated and in the RCC ISR
80 routine the system clock will be reconfigured to its previous state (before
81 HSE clock failure) */
82 }
83 }
84
85 /**
86 * @brief This function handles Hard Fault exception.
87 * @param None
88 * @retval None
89 */
90 void HardFault_Handler(void)
91 {
92 /* Go to infinite loop when Hard Fault exception occurs */
93 while (1)
94 {
95 }
96 }
97
98 /**
99 * @brief This function handles Memory Manage exception.
100 * @param None
101 * @retval None
102 */
103 void MemManage_Handler(void)
104 {
105 /* Go to infinite loop when Memory Manage exception occurs */
106 while (1)
107 {
108 }
109 }
110
111 /**
112 * @brief This function handles Bus Fault exception.
113 * @param None
114 * @retval None
115 */
116 void BusFault_Handler(void)
117 {
118 /* Go to infinite loop when Bus Fault exception occurs */
119 while (1)
120 {
121 }
122 }
123
124 /**
125 * @brief This function handles Usage Fault exception.
126 * @param None
127 * @retval None
128 */
129 void UsageFault_Handler(void)
130 {
131 /* Go to infinite loop when Usage Fault exception occurs */
132 while (1)
133 {
134 }
135 }
136
137 /**
138 * @brief This function handles SVCall exception.
139 * @param None
140 * @retval None
141 */
142 void SVC_Handler(void)
143 {
144 }
145
146 /**
147 * @brief This function handles Debug Monitor exception.
148 * @param None
149 * @retval None
150 */
151 void DebugMon_Handler(void)
152 {
153 }
154
155 /**
156 * @brief This function handles PendSV_Handler exception.
157 * @param None
158 * @retval None
159 */
160 void PendSV_Handler(void)
161 {
162 }
163
164 /**
165 * @brief This function handles SysTick Handler.
166 * @param None
167 * @retval None
168 */
169 void SysTick_Handler(void)
170 {
171 }
172
173 /******************************************************************************/
174 /* STM32F10x Peripherals Interrupt Handlers */
175 /******************************************************************************/
176
177 /**
178 * @brief This function handles RCC interrupt request.
179 * @param None
180 * @retval None
181 */
182 void RCC_IRQHandler(void)
183 {
184 if(RCC_GetITStatus(RCC_IT_HSERDY) != RESET)
185 {
186 /* Clear HSERDY interrupt pending bit */
187 RCC_ClearITPendingBit(RCC_IT_HSERDY);
188
189 /* Check if the HSE clock is still available */
190 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
191 {
192 #ifdef SYSCLK_HSE
193 /* Select HSE as system clock source */
194 RCC_SYSCLKConfig(RCC_SYSCLKSource_HSE);
195 #else
196 #ifdef STM32F10X_CL
197 /* Enable PLL2 */
198 RCC_PLL2Cmd(ENABLE);
199 #else
200 /* Enable PLL: once the PLL is ready the PLLRDY interrupt is generated */
201 RCC_PLLCmd(ENABLE);
202 #endif /* STM32F10X_CL */
203 #endif /* SYSCLK_HSE */
204 }
205 }
206
207 #ifdef STM32F10X_CL
208 if(RCC_GetITStatus(RCC_IT_PLL2RDY) != RESET)
209 {
210 /* Clear PLL2RDY interrupt pending bit */
211 RCC_ClearITPendingBit(RCC_IT_PLL2RDY);
212
213 /* Enable PLL: once the PLL is ready the PLLRDY interrupt is generated */
214 RCC_PLLCmd(ENABLE);
215 }
216 #endif /* STM32F10X_CL */
217
218 if(RCC_GetITStatus(RCC_IT_PLLRDY) != RESET)
219 {
220 /* Clear PLLRDY interrupt pending bit */
221 RCC_ClearITPendingBit(RCC_IT_PLLRDY);
222
223 /* Check if the PLL is still locked */
224 if (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) != RESET)
225 {
226 /* Select PLL as system clock source */
227 RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
228 }
229 }
230 }
231
232 /******************************************************************************/
233 /* STM32F10x Peripherals Interrupt Handlers */
234 /* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
235 /* available peripheral interrupt handler's name please refer to the startup */
236 /* file (startup_stm32f10x_xx.s). */
237 /******************************************************************************/
238
239 /**
240 * @brief This function handles PPP interrupt request.
241 * @param None
242 * @retval None
243 */
244 /*void PPP_IRQHandler(void)
245 {
246 }*/
247
248 /**
249 * @}
250 */
251
252 /**
253 * @}
254 */
255
256 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/