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comparison libs/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s @ 0:c59513fd84fb
Initial commit of STM32 test code.
author | Daniel O'Connor <darius@dons.net.au> |
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date | Mon, 03 Oct 2011 21:19:15 +1030 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file startup_stm32f10x_md.s | |
4 * @author MCD Application Team | |
5 * @version V3.5.0 | |
6 * @date 11-March-2011 | |
7 * @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain. | |
8 * This module performs: | |
9 * - Set the initial SP | |
10 * - Set the initial PC == Reset_Handler, | |
11 * - Set the vector table entries with the exceptions ISR address | |
12 * - Configure the clock system | |
13 * - Branches to main in the C library (which eventually | |
14 * calls main()). | |
15 * After Reset the Cortex-M3 processor is in Thread mode, | |
16 * priority is Privileged, and the Stack is set to Main. | |
17 ****************************************************************************** | |
18 * @attention | |
19 * | |
20 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS | |
21 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE | |
22 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY | |
23 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING | |
24 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE | |
25 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. | |
26 * | |
27 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> | |
28 ****************************************************************************** | |
29 */ | |
30 | |
31 .syntax unified | |
32 .cpu cortex-m3 | |
33 .fpu softvfp | |
34 .thumb | |
35 | |
36 .global g_pfnVectors | |
37 .global Default_Handler | |
38 | |
39 /* start address for the initialization values of the .data section. | |
40 defined in linker script */ | |
41 .word _sidata | |
42 /* start address for the .data section. defined in linker script */ | |
43 .word _sdata | |
44 /* end address for the .data section. defined in linker script */ | |
45 .word _edata | |
46 /* start address for the .bss section. defined in linker script */ | |
47 .word _sbss | |
48 /* end address for the .bss section. defined in linker script */ | |
49 .word _ebss | |
50 | |
51 .equ BootRAM, 0xF108F85F | |
52 /** | |
53 * @brief This is the code that gets called when the processor first | |
54 * starts execution following a reset event. Only the absolutely | |
55 * necessary set is performed, after which the application | |
56 * supplied main() routine is called. | |
57 * @param None | |
58 * @retval : None | |
59 */ | |
60 | |
61 .section .text.Reset_Handler | |
62 .weak Reset_Handler | |
63 .type Reset_Handler, %function | |
64 Reset_Handler: | |
65 | |
66 /* Copy the data segment initializers from flash to SRAM */ | |
67 movs r1, #0 | |
68 b LoopCopyDataInit | |
69 | |
70 CopyDataInit: | |
71 ldr r3, =_sidata | |
72 ldr r3, [r3, r1] | |
73 str r3, [r0, r1] | |
74 adds r1, r1, #4 | |
75 | |
76 LoopCopyDataInit: | |
77 ldr r0, =_sdata | |
78 ldr r3, =_edata | |
79 adds r2, r0, r1 | |
80 cmp r2, r3 | |
81 bcc CopyDataInit | |
82 ldr r2, =_sbss | |
83 b LoopFillZerobss | |
84 /* Zero fill the bss segment. */ | |
85 FillZerobss: | |
86 movs r3, #0 | |
87 str r3, [r2], #4 | |
88 | |
89 LoopFillZerobss: | |
90 ldr r3, = _ebss | |
91 cmp r2, r3 | |
92 bcc FillZerobss | |
93 /* Call the clock system intitialization function.*/ | |
94 bl SystemInit | |
95 /* Call the application's entry point.*/ | |
96 bl main | |
97 bx lr | |
98 .size Reset_Handler, .-Reset_Handler | |
99 | |
100 /** | |
101 * @brief This is the code that gets called when the processor receives an | |
102 * unexpected interrupt. This simply enters an infinite loop, preserving | |
103 * the system state for examination by a debugger. | |
104 * @param None | |
105 * @retval None | |
106 */ | |
107 .section .text.Default_Handler,"ax",%progbits | |
108 Default_Handler: | |
109 Infinite_Loop: | |
110 b Infinite_Loop | |
111 .size Default_Handler, .-Default_Handler | |
112 /****************************************************************************** | |
113 * | |
114 * The minimal vector table for a Cortex M3. Note that the proper constructs | |
115 * must be placed on this to ensure that it ends up at physical address | |
116 * 0x0000.0000. | |
117 * | |
118 ******************************************************************************/ | |
119 .section .isr_vector,"a",%progbits | |
120 .type g_pfnVectors, %object | |
121 .size g_pfnVectors, .-g_pfnVectors | |
122 | |
123 | |
124 g_pfnVectors: | |
125 .word _estack | |
126 .word Reset_Handler | |
127 .word NMI_Handler | |
128 .word HardFault_Handler | |
129 .word MemManage_Handler | |
130 .word BusFault_Handler | |
131 .word UsageFault_Handler | |
132 .word 0 | |
133 .word 0 | |
134 .word 0 | |
135 .word 0 | |
136 .word SVC_Handler | |
137 .word DebugMon_Handler | |
138 .word 0 | |
139 .word PendSV_Handler | |
140 .word SysTick_Handler | |
141 .word WWDG_IRQHandler | |
142 .word PVD_IRQHandler | |
143 .word TAMPER_IRQHandler | |
144 .word RTC_IRQHandler | |
145 .word FLASH_IRQHandler | |
146 .word RCC_IRQHandler | |
147 .word EXTI0_IRQHandler | |
148 .word EXTI1_IRQHandler | |
149 .word EXTI2_IRQHandler | |
150 .word EXTI3_IRQHandler | |
151 .word EXTI4_IRQHandler | |
152 .word DMA1_Channel1_IRQHandler | |
153 .word DMA1_Channel2_IRQHandler | |
154 .word DMA1_Channel3_IRQHandler | |
155 .word DMA1_Channel4_IRQHandler | |
156 .word DMA1_Channel5_IRQHandler | |
157 .word DMA1_Channel6_IRQHandler | |
158 .word DMA1_Channel7_IRQHandler | |
159 .word ADC1_2_IRQHandler | |
160 .word USB_HP_CAN1_TX_IRQHandler | |
161 .word USB_LP_CAN1_RX0_IRQHandler | |
162 .word CAN1_RX1_IRQHandler | |
163 .word CAN1_SCE_IRQHandler | |
164 .word EXTI9_5_IRQHandler | |
165 .word TIM1_BRK_IRQHandler | |
166 .word TIM1_UP_IRQHandler | |
167 .word TIM1_TRG_COM_IRQHandler | |
168 .word TIM1_CC_IRQHandler | |
169 .word TIM2_IRQHandler | |
170 .word TIM3_IRQHandler | |
171 .word TIM4_IRQHandler | |
172 .word I2C1_EV_IRQHandler | |
173 .word I2C1_ER_IRQHandler | |
174 .word I2C2_EV_IRQHandler | |
175 .word I2C2_ER_IRQHandler | |
176 .word SPI1_IRQHandler | |
177 .word SPI2_IRQHandler | |
178 .word USART1_IRQHandler | |
179 .word USART2_IRQHandler | |
180 .word USART3_IRQHandler | |
181 .word EXTI15_10_IRQHandler | |
182 .word RTCAlarm_IRQHandler | |
183 .word USBWakeUp_IRQHandler | |
184 .word 0 | |
185 .word 0 | |
186 .word 0 | |
187 .word 0 | |
188 .word 0 | |
189 .word 0 | |
190 .word 0 | |
191 .word BootRAM /* @0x108. This is for boot in RAM mode for | |
192 STM32F10x Medium Density devices. */ | |
193 | |
194 /******************************************************************************* | |
195 * | |
196 * Provide weak aliases for each Exception handler to the Default_Handler. | |
197 * As they are weak aliases, any function with the same name will override | |
198 * this definition. | |
199 * | |
200 *******************************************************************************/ | |
201 | |
202 .weak NMI_Handler | |
203 .thumb_set NMI_Handler,Default_Handler | |
204 | |
205 .weak HardFault_Handler | |
206 .thumb_set HardFault_Handler,Default_Handler | |
207 | |
208 .weak MemManage_Handler | |
209 .thumb_set MemManage_Handler,Default_Handler | |
210 | |
211 .weak BusFault_Handler | |
212 .thumb_set BusFault_Handler,Default_Handler | |
213 | |
214 .weak UsageFault_Handler | |
215 .thumb_set UsageFault_Handler,Default_Handler | |
216 | |
217 .weak SVC_Handler | |
218 .thumb_set SVC_Handler,Default_Handler | |
219 | |
220 .weak DebugMon_Handler | |
221 .thumb_set DebugMon_Handler,Default_Handler | |
222 | |
223 .weak PendSV_Handler | |
224 .thumb_set PendSV_Handler,Default_Handler | |
225 | |
226 .weak SysTick_Handler | |
227 .thumb_set SysTick_Handler,Default_Handler | |
228 | |
229 .weak WWDG_IRQHandler | |
230 .thumb_set WWDG_IRQHandler,Default_Handler | |
231 | |
232 .weak PVD_IRQHandler | |
233 .thumb_set PVD_IRQHandler,Default_Handler | |
234 | |
235 .weak TAMPER_IRQHandler | |
236 .thumb_set TAMPER_IRQHandler,Default_Handler | |
237 | |
238 .weak RTC_IRQHandler | |
239 .thumb_set RTC_IRQHandler,Default_Handler | |
240 | |
241 .weak FLASH_IRQHandler | |
242 .thumb_set FLASH_IRQHandler,Default_Handler | |
243 | |
244 .weak RCC_IRQHandler | |
245 .thumb_set RCC_IRQHandler,Default_Handler | |
246 | |
247 .weak EXTI0_IRQHandler | |
248 .thumb_set EXTI0_IRQHandler,Default_Handler | |
249 | |
250 .weak EXTI1_IRQHandler | |
251 .thumb_set EXTI1_IRQHandler,Default_Handler | |
252 | |
253 .weak EXTI2_IRQHandler | |
254 .thumb_set EXTI2_IRQHandler,Default_Handler | |
255 | |
256 .weak EXTI3_IRQHandler | |
257 .thumb_set EXTI3_IRQHandler,Default_Handler | |
258 | |
259 .weak EXTI4_IRQHandler | |
260 .thumb_set EXTI4_IRQHandler,Default_Handler | |
261 | |
262 .weak DMA1_Channel1_IRQHandler | |
263 .thumb_set DMA1_Channel1_IRQHandler,Default_Handler | |
264 | |
265 .weak DMA1_Channel2_IRQHandler | |
266 .thumb_set DMA1_Channel2_IRQHandler,Default_Handler | |
267 | |
268 .weak DMA1_Channel3_IRQHandler | |
269 .thumb_set DMA1_Channel3_IRQHandler,Default_Handler | |
270 | |
271 .weak DMA1_Channel4_IRQHandler | |
272 .thumb_set DMA1_Channel4_IRQHandler,Default_Handler | |
273 | |
274 .weak DMA1_Channel5_IRQHandler | |
275 .thumb_set DMA1_Channel5_IRQHandler,Default_Handler | |
276 | |
277 .weak DMA1_Channel6_IRQHandler | |
278 .thumb_set DMA1_Channel6_IRQHandler,Default_Handler | |
279 | |
280 .weak DMA1_Channel7_IRQHandler | |
281 .thumb_set DMA1_Channel7_IRQHandler,Default_Handler | |
282 | |
283 .weak ADC1_2_IRQHandler | |
284 .thumb_set ADC1_2_IRQHandler,Default_Handler | |
285 | |
286 .weak USB_HP_CAN1_TX_IRQHandler | |
287 .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler | |
288 | |
289 .weak USB_LP_CAN1_RX0_IRQHandler | |
290 .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler | |
291 | |
292 .weak CAN1_RX1_IRQHandler | |
293 .thumb_set CAN1_RX1_IRQHandler,Default_Handler | |
294 | |
295 .weak CAN1_SCE_IRQHandler | |
296 .thumb_set CAN1_SCE_IRQHandler,Default_Handler | |
297 | |
298 .weak EXTI9_5_IRQHandler | |
299 .thumb_set EXTI9_5_IRQHandler,Default_Handler | |
300 | |
301 .weak TIM1_BRK_IRQHandler | |
302 .thumb_set TIM1_BRK_IRQHandler,Default_Handler | |
303 | |
304 .weak TIM1_UP_IRQHandler | |
305 .thumb_set TIM1_UP_IRQHandler,Default_Handler | |
306 | |
307 .weak TIM1_TRG_COM_IRQHandler | |
308 .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler | |
309 | |
310 .weak TIM1_CC_IRQHandler | |
311 .thumb_set TIM1_CC_IRQHandler,Default_Handler | |
312 | |
313 .weak TIM2_IRQHandler | |
314 .thumb_set TIM2_IRQHandler,Default_Handler | |
315 | |
316 .weak TIM3_IRQHandler | |
317 .thumb_set TIM3_IRQHandler,Default_Handler | |
318 | |
319 .weak TIM4_IRQHandler | |
320 .thumb_set TIM4_IRQHandler,Default_Handler | |
321 | |
322 .weak I2C1_EV_IRQHandler | |
323 .thumb_set I2C1_EV_IRQHandler,Default_Handler | |
324 | |
325 .weak I2C1_ER_IRQHandler | |
326 .thumb_set I2C1_ER_IRQHandler,Default_Handler | |
327 | |
328 .weak I2C2_EV_IRQHandler | |
329 .thumb_set I2C2_EV_IRQHandler,Default_Handler | |
330 | |
331 .weak I2C2_ER_IRQHandler | |
332 .thumb_set I2C2_ER_IRQHandler,Default_Handler | |
333 | |
334 .weak SPI1_IRQHandler | |
335 .thumb_set SPI1_IRQHandler,Default_Handler | |
336 | |
337 .weak SPI2_IRQHandler | |
338 .thumb_set SPI2_IRQHandler,Default_Handler | |
339 | |
340 .weak USART1_IRQHandler | |
341 .thumb_set USART1_IRQHandler,Default_Handler | |
342 | |
343 .weak USART2_IRQHandler | |
344 .thumb_set USART2_IRQHandler,Default_Handler | |
345 | |
346 .weak USART3_IRQHandler | |
347 .thumb_set USART3_IRQHandler,Default_Handler | |
348 | |
349 .weak EXTI15_10_IRQHandler | |
350 .thumb_set EXTI15_10_IRQHandler,Default_Handler | |
351 | |
352 .weak RTCAlarm_IRQHandler | |
353 .thumb_set RTCAlarm_IRQHandler,Default_Handler | |
354 | |
355 .weak USBWakeUp_IRQHandler | |
356 .thumb_set USBWakeUp_IRQHandler,Default_Handler | |
357 | |
358 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |