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comparison libs/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s @ 0:c59513fd84fb
Initial commit of STM32 test code.
author | Daniel O'Connor <darius@dons.net.au> |
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date | Mon, 03 Oct 2011 21:19:15 +1030 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file startup_stm32f10x_ld_vl.s | |
4 * @author MCD Application Team | |
5 * @version V3.5.0 | |
6 * @date 11-March-2011 | |
7 * @brief STM32F10x Low Density Value Line Devices vector table for RIDE7 | |
8 * toolchain. | |
9 * This module performs: | |
10 * - Set the initial SP | |
11 * - Set the initial PC == Reset_Handler, | |
12 * - Set the vector table entries with the exceptions ISR address | |
13 * - Configure the clock system | |
14 * - Branches to main in the C library (which eventually | |
15 * calls main()). | |
16 * After Reset the Cortex-M3 processor is in Thread mode, | |
17 * priority is Privileged, and the Stack is set to Main. | |
18 ****************************************************************************** | |
19 * @attention | |
20 * | |
21 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS | |
22 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE | |
23 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY | |
24 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING | |
25 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE | |
26 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. | |
27 * | |
28 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> | |
29 ****************************************************************************** | |
30 */ | |
31 | |
32 .syntax unified | |
33 .cpu cortex-m3 | |
34 .fpu softvfp | |
35 .thumb | |
36 | |
37 .global g_pfnVectors | |
38 .global Default_Handler | |
39 | |
40 /* start address for the initialization values of the .data section. | |
41 defined in linker script */ | |
42 .word _sidata | |
43 /* start address for the .data section. defined in linker script */ | |
44 .word _sdata | |
45 /* end address for the .data section. defined in linker script */ | |
46 .word _edata | |
47 /* start address for the .bss section. defined in linker script */ | |
48 .word _sbss | |
49 /* end address for the .bss section. defined in linker script */ | |
50 .word _ebss | |
51 | |
52 .equ BootRAM, 0xF108F85F | |
53 /** | |
54 * @brief This is the code that gets called when the processor first | |
55 * starts execution following a reset event. Only the absolutely | |
56 * necessary set is performed, after which the application | |
57 * supplied main() routine is called. | |
58 * @param None | |
59 * @retval None | |
60 */ | |
61 | |
62 .section .text.Reset_Handler | |
63 .weak Reset_Handler | |
64 .type Reset_Handler, %function | |
65 Reset_Handler: | |
66 | |
67 /* Copy the data segment initializers from flash to SRAM */ | |
68 movs r1, #0 | |
69 b LoopCopyDataInit | |
70 | |
71 CopyDataInit: | |
72 ldr r3, =_sidata | |
73 ldr r3, [r3, r1] | |
74 str r3, [r0, r1] | |
75 adds r1, r1, #4 | |
76 | |
77 LoopCopyDataInit: | |
78 ldr r0, =_sdata | |
79 ldr r3, =_edata | |
80 adds r2, r0, r1 | |
81 cmp r2, r3 | |
82 bcc CopyDataInit | |
83 ldr r2, =_sbss | |
84 b LoopFillZerobss | |
85 /* Zero fill the bss segment. */ | |
86 FillZerobss: | |
87 movs r3, #0 | |
88 str r3, [r2], #4 | |
89 | |
90 LoopFillZerobss: | |
91 ldr r3, = _ebss | |
92 cmp r2, r3 | |
93 bcc FillZerobss | |
94 /* Call the clock system intitialization function.*/ | |
95 bl SystemInit | |
96 /* Call the application's entry point.*/ | |
97 bl main | |
98 bx lr | |
99 .size Reset_Handler, .-Reset_Handler | |
100 | |
101 /** | |
102 * @brief This is the code that gets called when the processor receives an | |
103 * unexpected interrupt. This simply enters an infinite loop, preserving | |
104 * the system state for examination by a debugger. | |
105 * @param None | |
106 * @retval None | |
107 */ | |
108 .section .text.Default_Handler,"ax",%progbits | |
109 Default_Handler: | |
110 Infinite_Loop: | |
111 b Infinite_Loop | |
112 .size Default_Handler, .-Default_Handler | |
113 /****************************************************************************** | |
114 * The minimal vector table for a Cortex M3. Note that the proper constructs | |
115 * must be placed on this to ensure that it ends up at physical address | |
116 * 0x0000.0000. | |
117 * | |
118 ******************************************************************************/ | |
119 .section .isr_vector,"a",%progbits | |
120 .type g_pfnVectors, %object | |
121 .size g_pfnVectors, .-g_pfnVectors | |
122 | |
123 g_pfnVectors: | |
124 .word _estack | |
125 .word Reset_Handler | |
126 .word NMI_Handler | |
127 .word HardFault_Handler | |
128 .word MemManage_Handler | |
129 .word BusFault_Handler | |
130 .word UsageFault_Handler | |
131 .word 0 | |
132 .word 0 | |
133 .word 0 | |
134 .word 0 | |
135 .word SVC_Handler | |
136 .word DebugMon_Handler | |
137 .word 0 | |
138 .word PendSV_Handler | |
139 .word SysTick_Handler | |
140 .word WWDG_IRQHandler | |
141 .word PVD_IRQHandler | |
142 .word TAMPER_IRQHandler | |
143 .word RTC_IRQHandler | |
144 .word FLASH_IRQHandler | |
145 .word RCC_IRQHandler | |
146 .word EXTI0_IRQHandler | |
147 .word EXTI1_IRQHandler | |
148 .word EXTI2_IRQHandler | |
149 .word EXTI3_IRQHandler | |
150 .word EXTI4_IRQHandler | |
151 .word DMA1_Channel1_IRQHandler | |
152 .word DMA1_Channel2_IRQHandler | |
153 .word DMA1_Channel3_IRQHandler | |
154 .word DMA1_Channel4_IRQHandler | |
155 .word DMA1_Channel5_IRQHandler | |
156 .word DMA1_Channel6_IRQHandler | |
157 .word DMA1_Channel7_IRQHandler | |
158 .word ADC1_IRQHandler | |
159 .word 0 | |
160 .word 0 | |
161 .word 0 | |
162 .word 0 | |
163 .word EXTI9_5_IRQHandler | |
164 .word TIM1_BRK_TIM15_IRQHandler | |
165 .word TIM1_UP_TIM16_IRQHandler | |
166 .word TIM1_TRG_COM_TIM17_IRQHandler | |
167 .word TIM1_CC_IRQHandler | |
168 .word TIM2_IRQHandler | |
169 .word TIM3_IRQHandler | |
170 .word 0 | |
171 .word I2C1_EV_IRQHandler | |
172 .word I2C1_ER_IRQHandler | |
173 .word 0 | |
174 .word 0 | |
175 .word SPI1_IRQHandler | |
176 .word 0 | |
177 .word USART1_IRQHandler | |
178 .word USART2_IRQHandler | |
179 .word 0 | |
180 .word EXTI15_10_IRQHandler | |
181 .word RTCAlarm_IRQHandler | |
182 .word CEC_IRQHandler | |
183 .word 0 | |
184 .word 0 | |
185 .word 0 | |
186 .word 0 | |
187 .word 0 | |
188 .word 0 | |
189 .word 0 | |
190 .word 0 | |
191 .word 0 | |
192 .word 0 | |
193 .word 0 | |
194 .word TIM6_DAC_IRQHandler | |
195 .word TIM7_IRQHandler | |
196 .word 0 | |
197 .word 0 | |
198 .word 0 | |
199 .word 0 | |
200 .word 0 | |
201 .word 0 | |
202 .word 0 | |
203 .word 0 | |
204 .word 0 | |
205 .word 0 | |
206 .word 0 | |
207 .word 0 | |
208 .word 0 | |
209 .word 0 | |
210 .word 0 | |
211 .word 0 | |
212 .word 0 | |
213 .word 0 | |
214 .word 0 | |
215 .word 0 | |
216 .word 0 | |
217 .word 0 | |
218 .word 0 | |
219 .word 0 | |
220 .word 0 | |
221 .word 0 | |
222 .word 0 | |
223 .word 0 | |
224 .word 0 | |
225 .word 0 | |
226 .word 0 | |
227 .word 0 | |
228 .word 0 | |
229 .word 0 | |
230 .word 0 | |
231 .word 0 | |
232 .word 0 | |
233 .word 0 | |
234 .word 0 | |
235 .word 0 | |
236 .word 0 | |
237 .word 0 | |
238 .word 0 | |
239 .word BootRAM /* @0x01CC. This is for boot in RAM mode for | |
240 STM32F10x Low Density Value Line devices. */ | |
241 | |
242 /******************************************************************************* | |
243 * Provide weak aliases for each Exception handler to the Default_Handler. | |
244 * As they are weak aliases, any function with the same name will override | |
245 * this definition. | |
246 *******************************************************************************/ | |
247 | |
248 .weak NMI_Handler | |
249 .thumb_set NMI_Handler,Default_Handler | |
250 | |
251 .weak HardFault_Handler | |
252 .thumb_set HardFault_Handler,Default_Handler | |
253 | |
254 .weak MemManage_Handler | |
255 .thumb_set MemManage_Handler,Default_Handler | |
256 | |
257 .weak BusFault_Handler | |
258 .thumb_set BusFault_Handler,Default_Handler | |
259 | |
260 .weak UsageFault_Handler | |
261 .thumb_set UsageFault_Handler,Default_Handler | |
262 | |
263 .weak SVC_Handler | |
264 .thumb_set SVC_Handler,Default_Handler | |
265 | |
266 .weak DebugMon_Handler | |
267 .thumb_set DebugMon_Handler,Default_Handler | |
268 | |
269 .weak PendSV_Handler | |
270 .thumb_set PendSV_Handler,Default_Handler | |
271 | |
272 .weak SysTick_Handler | |
273 .thumb_set SysTick_Handler,Default_Handler | |
274 | |
275 .weak WWDG_IRQHandler | |
276 .thumb_set WWDG_IRQHandler,Default_Handler | |
277 | |
278 .weak PVD_IRQHandler | |
279 .thumb_set PVD_IRQHandler,Default_Handler | |
280 | |
281 .weak TAMPER_IRQHandler | |
282 .thumb_set TAMPER_IRQHandler,Default_Handler | |
283 | |
284 .weak RTC_IRQHandler | |
285 .thumb_set RTC_IRQHandler,Default_Handler | |
286 | |
287 .weak FLASH_IRQHandler | |
288 .thumb_set FLASH_IRQHandler,Default_Handler | |
289 | |
290 .weak RCC_IRQHandler | |
291 .thumb_set RCC_IRQHandler,Default_Handler | |
292 | |
293 .weak EXTI0_IRQHandler | |
294 .thumb_set EXTI0_IRQHandler,Default_Handler | |
295 | |
296 .weak EXTI1_IRQHandler | |
297 .thumb_set EXTI1_IRQHandler,Default_Handler | |
298 | |
299 .weak EXTI2_IRQHandler | |
300 .thumb_set EXTI2_IRQHandler,Default_Handler | |
301 | |
302 .weak EXTI3_IRQHandler | |
303 .thumb_set EXTI3_IRQHandler,Default_Handler | |
304 | |
305 .weak EXTI4_IRQHandler | |
306 .thumb_set EXTI4_IRQHandler,Default_Handler | |
307 | |
308 .weak DMA1_Channel1_IRQHandler | |
309 .thumb_set DMA1_Channel1_IRQHandler,Default_Handler | |
310 | |
311 .weak DMA1_Channel2_IRQHandler | |
312 .thumb_set DMA1_Channel2_IRQHandler,Default_Handler | |
313 | |
314 .weak DMA1_Channel3_IRQHandler | |
315 .thumb_set DMA1_Channel3_IRQHandler,Default_Handler | |
316 | |
317 .weak DMA1_Channel4_IRQHandler | |
318 .thumb_set DMA1_Channel4_IRQHandler,Default_Handler | |
319 | |
320 .weak DMA1_Channel5_IRQHandler | |
321 .thumb_set DMA1_Channel5_IRQHandler,Default_Handler | |
322 | |
323 .weak DMA1_Channel6_IRQHandler | |
324 .thumb_set DMA1_Channel6_IRQHandler,Default_Handler | |
325 | |
326 .weak DMA1_Channel7_IRQHandler | |
327 .thumb_set DMA1_Channel7_IRQHandler,Default_Handler | |
328 | |
329 .weak ADC1_IRQHandler | |
330 .thumb_set ADC1_IRQHandler,Default_Handler | |
331 | |
332 .weak EXTI9_5_IRQHandler | |
333 .thumb_set EXTI9_5_IRQHandler,Default_Handler | |
334 | |
335 .weak TIM1_BRK_TIM15_IRQHandler | |
336 .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler | |
337 | |
338 .weak TIM1_UP_TIM16_IRQHandler | |
339 .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler | |
340 | |
341 .weak TIM1_TRG_COM_TIM17_IRQHandler | |
342 .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler | |
343 | |
344 .weak TIM1_CC_IRQHandler | |
345 .thumb_set TIM1_CC_IRQHandler,Default_Handler | |
346 | |
347 .weak TIM2_IRQHandler | |
348 .thumb_set TIM2_IRQHandler,Default_Handler | |
349 | |
350 .weak TIM3_IRQHandler | |
351 .thumb_set TIM3_IRQHandler,Default_Handler | |
352 | |
353 .weak I2C1_EV_IRQHandler | |
354 .thumb_set I2C1_EV_IRQHandler,Default_Handler | |
355 | |
356 .weak I2C1_ER_IRQHandler | |
357 .thumb_set I2C1_ER_IRQHandler,Default_Handler | |
358 | |
359 .weak SPI1_IRQHandler | |
360 .thumb_set SPI1_IRQHandler,Default_Handler | |
361 | |
362 .weak USART1_IRQHandler | |
363 .thumb_set USART1_IRQHandler,Default_Handler | |
364 | |
365 .weak USART2_IRQHandler | |
366 .thumb_set USART2_IRQHandler,Default_Handler | |
367 | |
368 .weak EXTI15_10_IRQHandler | |
369 .thumb_set EXTI15_10_IRQHandler,Default_Handler | |
370 | |
371 .weak RTCAlarm_IRQHandler | |
372 .thumb_set RTCAlarm_IRQHandler,Default_Handler | |
373 | |
374 .weak CEC_IRQHandler | |
375 .thumb_set CEC_IRQHandler,Default_Handler | |
376 | |
377 .weak TIM6_DAC_IRQHandler | |
378 .thumb_set TIM6_DAC_IRQHandler,Default_Handler | |
379 | |
380 .weak TIM7_IRQHandler | |
381 .thumb_set TIM7_IRQHandler,Default_Handler | |
382 | |
383 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |