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comparison libs/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s @ 0:c59513fd84fb
Initial commit of STM32 test code.
author | Daniel O'Connor <darius@dons.net.au> |
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date | Mon, 03 Oct 2011 21:19:15 +1030 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file startup_stm32f10x_hd_vl.s | |
4 * @author MCD Application Team | |
5 * @version V3.5.0 | |
6 * @date 11-March-2011 | |
7 * @brief STM32F10x High Density Value Line Devices vector table for RIDE7 | |
8 * toolchain. | |
9 * This module performs: | |
10 * - Set the initial SP | |
11 * - Set the initial PC == Reset_Handler, | |
12 * - Set the vector table entries with the exceptions ISR address | |
13 * - Configure the clock system and the external SRAM mounted on | |
14 * STM32100E-EVAL board to be used as data memory (optional, | |
15 * to be enabled by user) | |
16 * - Branches to main in the C library (which eventually | |
17 * calls main()). | |
18 * After Reset the Cortex-M3 processor is in Thread mode, | |
19 * priority is Privileged, and the Stack is set to Main. | |
20 ****************************************************************************** | |
21 * @attention | |
22 * | |
23 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS | |
24 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE | |
25 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY | |
26 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING | |
27 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE | |
28 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. | |
29 * | |
30 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> | |
31 ****************************************************************************** | |
32 */ | |
33 | |
34 .syntax unified | |
35 .cpu cortex-m3 | |
36 .fpu softvfp | |
37 .thumb | |
38 | |
39 .global g_pfnVectors | |
40 .global Default_Handler | |
41 | |
42 /* start address for the initialization values of the .data section. | |
43 defined in linker script */ | |
44 .word _sidata | |
45 /* start address for the .data section. defined in linker script */ | |
46 .word _sdata | |
47 /* end address for the .data section. defined in linker script */ | |
48 .word _edata | |
49 /* start address for the .bss section. defined in linker script */ | |
50 .word _sbss | |
51 /* end address for the .bss section. defined in linker script */ | |
52 .word _ebss | |
53 | |
54 .equ BootRAM, 0xF108F85F | |
55 /** | |
56 * @brief This is the code that gets called when the processor first | |
57 * starts execution following a reset event. Only the absolutely | |
58 * necessary set is performed, after which the application | |
59 * supplied main() routine is called. | |
60 * @param None | |
61 * @retval None | |
62 */ | |
63 | |
64 .section .text.Reset_Handler | |
65 .weak Reset_Handler | |
66 .type Reset_Handler, %function | |
67 Reset_Handler: | |
68 | |
69 /* Copy the data segment initializers from flash to SRAM */ | |
70 movs r1, #0 | |
71 b LoopCopyDataInit | |
72 | |
73 CopyDataInit: | |
74 ldr r3, =_sidata | |
75 ldr r3, [r3, r1] | |
76 str r3, [r0, r1] | |
77 adds r1, r1, #4 | |
78 | |
79 LoopCopyDataInit: | |
80 ldr r0, =_sdata | |
81 ldr r3, =_edata | |
82 adds r2, r0, r1 | |
83 cmp r2, r3 | |
84 bcc CopyDataInit | |
85 ldr r2, =_sbss | |
86 b LoopFillZerobss | |
87 /* Zero fill the bss segment. */ | |
88 FillZerobss: | |
89 movs r3, #0 | |
90 str r3, [r2], #4 | |
91 | |
92 LoopFillZerobss: | |
93 ldr r3, = _ebss | |
94 cmp r2, r3 | |
95 bcc FillZerobss | |
96 /* Call the clock system intitialization function.*/ | |
97 bl SystemInit | |
98 /* Call the application's entry point.*/ | |
99 bl main | |
100 bx lr | |
101 .size Reset_Handler, .-Reset_Handler | |
102 | |
103 /** | |
104 * @brief This is the code that gets called when the processor receives an | |
105 * unexpected interrupt. This simply enters an infinite loop, preserving | |
106 * the system state for examination by a debugger. | |
107 * @param None | |
108 * @retval None | |
109 */ | |
110 .section .text.Default_Handler,"ax",%progbits | |
111 Default_Handler: | |
112 Infinite_Loop: | |
113 b Infinite_Loop | |
114 .size Default_Handler, .-Default_Handler | |
115 /****************************************************************************** | |
116 * | |
117 * The minimal vector table for a Cortex M3. Note that the proper constructs | |
118 * must be placed on this to ensure that it ends up at physical address | |
119 * 0x0000.0000. | |
120 * | |
121 ******************************************************************************/ | |
122 .section .isr_vector,"a",%progbits | |
123 .type g_pfnVectors, %object | |
124 .size g_pfnVectors, .-g_pfnVectors | |
125 | |
126 g_pfnVectors: | |
127 .word _estack | |
128 .word Reset_Handler | |
129 .word NMI_Handler | |
130 .word HardFault_Handler | |
131 .word MemManage_Handler | |
132 .word BusFault_Handler | |
133 .word UsageFault_Handler | |
134 .word 0 | |
135 .word 0 | |
136 .word 0 | |
137 .word 0 | |
138 .word SVC_Handler | |
139 .word DebugMon_Handler | |
140 .word 0 | |
141 .word PendSV_Handler | |
142 .word SysTick_Handler | |
143 .word WWDG_IRQHandler | |
144 .word PVD_IRQHandler | |
145 .word TAMPER_IRQHandler | |
146 .word RTC_IRQHandler | |
147 .word FLASH_IRQHandler | |
148 .word RCC_IRQHandler | |
149 .word EXTI0_IRQHandler | |
150 .word EXTI1_IRQHandler | |
151 .word EXTI2_IRQHandler | |
152 .word EXTI3_IRQHandler | |
153 .word EXTI4_IRQHandler | |
154 .word DMA1_Channel1_IRQHandler | |
155 .word DMA1_Channel2_IRQHandler | |
156 .word DMA1_Channel3_IRQHandler | |
157 .word DMA1_Channel4_IRQHandler | |
158 .word DMA1_Channel5_IRQHandler | |
159 .word DMA1_Channel6_IRQHandler | |
160 .word DMA1_Channel7_IRQHandler | |
161 .word ADC1_IRQHandler | |
162 .word 0 | |
163 .word 0 | |
164 .word 0 | |
165 .word 0 | |
166 .word EXTI9_5_IRQHandler | |
167 .word TIM1_BRK_TIM15_IRQHandler | |
168 .word TIM1_UP_TIM16_IRQHandler | |
169 .word TIM1_TRG_COM_TIM17_IRQHandler | |
170 .word TIM1_CC_IRQHandler | |
171 .word TIM2_IRQHandler | |
172 .word TIM3_IRQHandler | |
173 .word TIM4_IRQHandler | |
174 .word I2C1_EV_IRQHandler | |
175 .word I2C1_ER_IRQHandler | |
176 .word I2C2_EV_IRQHandler | |
177 .word I2C2_ER_IRQHandler | |
178 .word SPI1_IRQHandler | |
179 .word SPI2_IRQHandler | |
180 .word USART1_IRQHandler | |
181 .word USART2_IRQHandler | |
182 .word USART3_IRQHandler | |
183 .word EXTI15_10_IRQHandler | |
184 .word RTCAlarm_IRQHandler | |
185 .word CEC_IRQHandler | |
186 .word TIM12_IRQHandler | |
187 .word TIM13_IRQHandler | |
188 .word TIM14_IRQHandler | |
189 .word 0 | |
190 .word 0 | |
191 .word 0 | |
192 .word 0 | |
193 .word TIM5_IRQHandler | |
194 .word SPI3_IRQHandler | |
195 .word UART4_IRQHandler | |
196 .word UART5_IRQHandler | |
197 .word TIM6_DAC_IRQHandler | |
198 .word TIM7_IRQHandler | |
199 .word DMA2_Channel1_IRQHandler | |
200 .word DMA2_Channel2_IRQHandler | |
201 .word DMA2_Channel3_IRQHandler | |
202 .word DMA2_Channel4_5_IRQHandler | |
203 .word DMA2_Channel5_IRQHandler | |
204 .word 0 | |
205 .word 0 | |
206 .word 0 | |
207 .word 0 | |
208 .word 0 | |
209 .word 0 | |
210 .word 0 | |
211 .word 0 | |
212 .word 0 | |
213 .word 0 | |
214 .word 0 | |
215 .word 0 | |
216 .word 0 | |
217 .word 0 | |
218 .word 0 | |
219 .word 0 | |
220 .word 0 | |
221 .word 0 | |
222 .word 0 | |
223 .word 0 | |
224 .word 0 | |
225 .word 0 | |
226 .word 0 | |
227 .word 0 | |
228 .word 0 | |
229 .word 0 | |
230 .word 0 | |
231 .word 0 | |
232 .word 0 | |
233 .word 0 | |
234 .word 0 | |
235 .word 0 | |
236 .word 0 | |
237 .word 0 | |
238 .word 0 | |
239 .word 0 | |
240 .word 0 | |
241 .word 0 | |
242 .word 0 | |
243 .word 0 | |
244 .word 0 | |
245 .word 0 | |
246 .word 0 | |
247 .word BootRAM /* @0x1E0. This is for boot in RAM mode for | |
248 STM32F10x High Density Value line devices. */ | |
249 | |
250 /******************************************************************************* | |
251 * Provide weak aliases for each Exception handler to the Default_Handler. | |
252 * As they are weak aliases, any function with the same name will override | |
253 * this definition. | |
254 *******************************************************************************/ | |
255 | |
256 .weak NMI_Handler | |
257 .thumb_set NMI_Handler,Default_Handler | |
258 | |
259 .weak HardFault_Handler | |
260 .thumb_set HardFault_Handler,Default_Handler | |
261 | |
262 .weak MemManage_Handler | |
263 .thumb_set MemManage_Handler,Default_Handler | |
264 | |
265 .weak BusFault_Handler | |
266 .thumb_set BusFault_Handler,Default_Handler | |
267 | |
268 .weak UsageFault_Handler | |
269 .thumb_set UsageFault_Handler,Default_Handler | |
270 | |
271 .weak SVC_Handler | |
272 .thumb_set SVC_Handler,Default_Handler | |
273 | |
274 .weak DebugMon_Handler | |
275 .thumb_set DebugMon_Handler,Default_Handler | |
276 | |
277 .weak PendSV_Handler | |
278 .thumb_set PendSV_Handler,Default_Handler | |
279 | |
280 .weak SysTick_Handler | |
281 .thumb_set SysTick_Handler,Default_Handler | |
282 | |
283 .weak WWDG_IRQHandler | |
284 .thumb_set WWDG_IRQHandler,Default_Handler | |
285 | |
286 .weak PVD_IRQHandler | |
287 .thumb_set PVD_IRQHandler,Default_Handler | |
288 | |
289 .weak TAMPER_IRQHandler | |
290 .thumb_set TAMPER_IRQHandler,Default_Handler | |
291 | |
292 .weak RTC_IRQHandler | |
293 .thumb_set RTC_IRQHandler,Default_Handler | |
294 | |
295 .weak FLASH_IRQHandler | |
296 .thumb_set FLASH_IRQHandler,Default_Handler | |
297 | |
298 .weak RCC_IRQHandler | |
299 .thumb_set RCC_IRQHandler,Default_Handler | |
300 | |
301 .weak EXTI0_IRQHandler | |
302 .thumb_set EXTI0_IRQHandler,Default_Handler | |
303 | |
304 .weak EXTI1_IRQHandler | |
305 .thumb_set EXTI1_IRQHandler,Default_Handler | |
306 | |
307 .weak EXTI2_IRQHandler | |
308 .thumb_set EXTI2_IRQHandler,Default_Handler | |
309 | |
310 .weak EXTI3_IRQHandler | |
311 .thumb_set EXTI3_IRQHandler,Default_Handler | |
312 | |
313 .weak EXTI4_IRQHandler | |
314 .thumb_set EXTI4_IRQHandler,Default_Handler | |
315 | |
316 .weak DMA1_Channel1_IRQHandler | |
317 .thumb_set DMA1_Channel1_IRQHandler,Default_Handler | |
318 | |
319 .weak DMA1_Channel2_IRQHandler | |
320 .thumb_set DMA1_Channel2_IRQHandler,Default_Handler | |
321 | |
322 .weak DMA1_Channel3_IRQHandler | |
323 .thumb_set DMA1_Channel3_IRQHandler,Default_Handler | |
324 | |
325 .weak DMA1_Channel4_IRQHandler | |
326 .thumb_set DMA1_Channel4_IRQHandler,Default_Handler | |
327 | |
328 .weak DMA1_Channel5_IRQHandler | |
329 .thumb_set DMA1_Channel5_IRQHandler,Default_Handler | |
330 | |
331 .weak DMA1_Channel6_IRQHandler | |
332 .thumb_set DMA1_Channel6_IRQHandler,Default_Handler | |
333 | |
334 .weak DMA1_Channel7_IRQHandler | |
335 .thumb_set DMA1_Channel7_IRQHandler,Default_Handler | |
336 | |
337 .weak ADC1_IRQHandler | |
338 .thumb_set ADC1_IRQHandler,Default_Handler | |
339 | |
340 .weak EXTI9_5_IRQHandler | |
341 .thumb_set EXTI9_5_IRQHandler,Default_Handler | |
342 | |
343 .weak TIM1_BRK_TIM15_IRQHandler | |
344 .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler | |
345 | |
346 .weak TIM1_UP_TIM16_IRQHandler | |
347 .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler | |
348 | |
349 .weak TIM1_TRG_COM_TIM17_IRQHandler | |
350 .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler | |
351 | |
352 .weak TIM1_CC_IRQHandler | |
353 .thumb_set TIM1_CC_IRQHandler,Default_Handler | |
354 | |
355 .weak TIM2_IRQHandler | |
356 .thumb_set TIM2_IRQHandler,Default_Handler | |
357 | |
358 .weak TIM3_IRQHandler | |
359 .thumb_set TIM3_IRQHandler,Default_Handler | |
360 | |
361 .weak TIM4_IRQHandler | |
362 .thumb_set TIM4_IRQHandler,Default_Handler | |
363 | |
364 .weak I2C1_EV_IRQHandler | |
365 .thumb_set I2C1_EV_IRQHandler,Default_Handler | |
366 | |
367 .weak I2C1_ER_IRQHandler | |
368 .thumb_set I2C1_ER_IRQHandler,Default_Handler | |
369 | |
370 .weak I2C2_EV_IRQHandler | |
371 .thumb_set I2C2_EV_IRQHandler,Default_Handler | |
372 | |
373 .weak I2C2_ER_IRQHandler | |
374 .thumb_set I2C2_ER_IRQHandler,Default_Handler | |
375 | |
376 .weak SPI1_IRQHandler | |
377 .thumb_set SPI1_IRQHandler,Default_Handler | |
378 | |
379 .weak SPI2_IRQHandler | |
380 .thumb_set SPI2_IRQHandler,Default_Handler | |
381 | |
382 .weak USART1_IRQHandler | |
383 .thumb_set USART1_IRQHandler,Default_Handler | |
384 | |
385 .weak USART2_IRQHandler | |
386 .thumb_set USART2_IRQHandler,Default_Handler | |
387 | |
388 .weak USART3_IRQHandler | |
389 .thumb_set USART3_IRQHandler,Default_Handler | |
390 | |
391 .weak EXTI15_10_IRQHandler | |
392 .thumb_set EXTI15_10_IRQHandler,Default_Handler | |
393 | |
394 .weak RTCAlarm_IRQHandler | |
395 .thumb_set RTCAlarm_IRQHandler,Default_Handler | |
396 | |
397 .weak CEC_IRQHandler | |
398 .thumb_set CEC_IRQHandler,Default_Handler | |
399 | |
400 .weak TIM12_IRQHandler | |
401 .thumb_set TIM12_IRQHandler,Default_Handler | |
402 | |
403 .weak TIM13_IRQHandler | |
404 .thumb_set TIM13_IRQHandler,Default_Handler | |
405 | |
406 .weak TIM14_IRQHandler | |
407 .thumb_set TIM14_IRQHandler,Default_Handler | |
408 | |
409 .weak TIM5_IRQHandler | |
410 .thumb_set TIM5_IRQHandler,Default_Handler | |
411 | |
412 .weak SPI3_IRQHandler | |
413 .thumb_set SPI3_IRQHandler,Default_Handler | |
414 | |
415 .weak UART4_IRQHandler | |
416 .thumb_set UART4_IRQHandler,Default_Handler | |
417 | |
418 .weak UART5_IRQHandler | |
419 .thumb_set UART5_IRQHandler,Default_Handler | |
420 | |
421 .weak TIM6_DAC_IRQHandler | |
422 .thumb_set TIM6_DAC_IRQHandler,Default_Handler | |
423 | |
424 .weak TIM7_IRQHandler | |
425 .thumb_set TIM7_IRQHandler,Default_Handler | |
426 | |
427 .weak DMA2_Channel1_IRQHandler | |
428 .thumb_set DMA2_Channel1_IRQHandler,Default_Handler | |
429 | |
430 .weak DMA2_Channel2_IRQHandler | |
431 .thumb_set DMA2_Channel2_IRQHandler,Default_Handler | |
432 | |
433 .weak DMA2_Channel3_IRQHandler | |
434 .thumb_set DMA2_Channel3_IRQHandler,Default_Handler | |
435 | |
436 .weak DMA2_Channel4_5_IRQHandler | |
437 .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler | |
438 | |
439 .weak DMA2_Channel5_IRQHandler | |
440 .thumb_set DMA2_Channel5_IRQHandler,Default_Handler | |
441 | |
442 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |