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Initial commit of STM32 test code.
author Daniel O'Connor <darius@dons.net.au>
date Mon, 03 Oct 2011 21:19:15 +1030
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1 ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
2 ;* File Name : startup_stm32f10x_hd_vl.s
3 ;* Author : MCD Application Team
4 ;* Version : V3.5.0
5 ;* Date : 11-March-2011
6 ;* Description : STM32F10x High Density Value Line Devices vector table
7 ;* for MDK-ARM toolchain.
8 ;* This module performs:
9 ;* - Set the initial SP
10 ;* - Set the initial PC == Reset_Handler
11 ;* - Set the vector table entries with the exceptions ISR address
12 ;* - Configure the clock system and also configure the external
13 ;* SRAM mounted on STM32100E-EVAL board to be used as data
14 ;* memory (optional, to be enabled by user)
15 ;* - Branches to __main in the C library (which eventually
16 ;* calls main()).
17 ;* After Reset the CortexM3 processor is in Thread mode,
18 ;* priority is Privileged, and the Stack is set to Main.
19 ;* <<< Use Configuration Wizard in Context Menu >>>
20 ;*******************************************************************************
21 ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
22 ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
23 ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
24 ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
25 ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
26 ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
27 ;*******************************************************************************
28
29 ; Amount of memory (in bytes) allocated for Stack
30 ; Tailor this value to your application needs
31 ; <h> Stack Configuration
32 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
33 ; </h>
34
35 Stack_Size EQU 0x00000400
36
37 AREA STACK, NOINIT, READWRITE, ALIGN=3
38 Stack_Mem SPACE Stack_Size
39 __initial_sp
40
41
42 ; <h> Heap Configuration
43 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
44 ; </h>
45
46 Heap_Size EQU 0x00000200
47
48 AREA HEAP, NOINIT, READWRITE, ALIGN=3
49 __heap_base
50 Heap_Mem SPACE Heap_Size
51 __heap_limit
52
53 PRESERVE8
54 THUMB
55
56
57 ; Vector Table Mapped to Address 0 at Reset
58 AREA RESET, DATA, READONLY
59 EXPORT __Vectors
60 EXPORT __Vectors_End
61 EXPORT __Vectors_Size
62
63 __Vectors DCD __initial_sp ; Top of Stack
64 DCD Reset_Handler ; Reset Handler
65 DCD NMI_Handler ; NMI Handler
66 DCD HardFault_Handler ; Hard Fault Handler
67 DCD MemManage_Handler ; MPU Fault Handler
68 DCD BusFault_Handler ; Bus Fault Handler
69 DCD UsageFault_Handler ; Usage Fault Handler
70 DCD 0 ; Reserved
71 DCD 0 ; Reserved
72 DCD 0 ; Reserved
73 DCD 0 ; Reserved
74 DCD SVC_Handler ; SVCall Handler
75 DCD DebugMon_Handler ; Debug Monitor Handler
76 DCD 0 ; Reserved
77 DCD PendSV_Handler ; PendSV Handler
78 DCD SysTick_Handler ; SysTick Handler
79
80 ; External Interrupts
81 DCD WWDG_IRQHandler ; Window Watchdog
82 DCD PVD_IRQHandler ; PVD through EXTI Line detect
83 DCD TAMPER_IRQHandler ; Tamper
84 DCD RTC_IRQHandler ; RTC
85 DCD FLASH_IRQHandler ; Flash
86 DCD RCC_IRQHandler ; RCC
87 DCD EXTI0_IRQHandler ; EXTI Line 0
88 DCD EXTI1_IRQHandler ; EXTI Line 1
89 DCD EXTI2_IRQHandler ; EXTI Line 2
90 DCD EXTI3_IRQHandler ; EXTI Line 3
91 DCD EXTI4_IRQHandler ; EXTI Line 4
92 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
93 DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
94 DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
95 DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
96 DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
97 DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
98 DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
99 DCD ADC1_IRQHandler ; ADC1
100 DCD 0 ; Reserved
101 DCD 0 ; Reserved
102 DCD 0 ; Reserved
103 DCD 0 ; Reserved
104 DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
105 DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
106 DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
107 DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
108 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
109 DCD TIM2_IRQHandler ; TIM2
110 DCD TIM3_IRQHandler ; TIM3
111 DCD TIM4_IRQHandler ; TIM4
112 DCD I2C1_EV_IRQHandler ; I2C1 Event
113 DCD I2C1_ER_IRQHandler ; I2C1 Error
114 DCD I2C2_EV_IRQHandler ; I2C2 Event
115 DCD I2C2_ER_IRQHandler ; I2C2 Error
116 DCD SPI1_IRQHandler ; SPI1
117 DCD SPI2_IRQHandler ; SPI2
118 DCD USART1_IRQHandler ; USART1
119 DCD USART2_IRQHandler ; USART2
120 DCD USART3_IRQHandler ; USART3
121 DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
122 DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
123 DCD CEC_IRQHandler ; HDMI-CEC
124 DCD TIM12_IRQHandler ; TIM12
125 DCD TIM13_IRQHandler ; TIM13
126 DCD TIM14_IRQHandler ; TIM14
127 DCD 0 ; Reserved
128 DCD 0 ; Reserved
129 DCD 0 ; Reserved
130 DCD 0 ; Reserved
131 DCD TIM5_IRQHandler ; TIM5
132 DCD SPI3_IRQHandler ; SPI3
133 DCD UART4_IRQHandler ; UART4
134 DCD UART5_IRQHandler ; UART5
135 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
136 DCD TIM7_IRQHandler ; TIM7
137 DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
138 DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
139 DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
140 DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
141 DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
142 __Vectors_End
143
144 __Vectors_Size EQU __Vectors_End - __Vectors
145
146 AREA |.text|, CODE, READONLY
147
148 ; Reset handler
149 Reset_Handler PROC
150 EXPORT Reset_Handler [WEAK]
151 IMPORT __main
152 IMPORT SystemInit
153 LDR R0, =SystemInit
154 BLX R0
155 LDR R0, =__main
156 BX R0
157 ENDP
158
159 ; Dummy Exception Handlers (infinite loops which can be modified)
160
161 NMI_Handler PROC
162 EXPORT NMI_Handler [WEAK]
163 B .
164 ENDP
165 HardFault_Handler\
166 PROC
167 EXPORT HardFault_Handler [WEAK]
168 B .
169 ENDP
170 MemManage_Handler\
171 PROC
172 EXPORT MemManage_Handler [WEAK]
173 B .
174 ENDP
175 BusFault_Handler\
176 PROC
177 EXPORT BusFault_Handler [WEAK]
178 B .
179 ENDP
180 UsageFault_Handler\
181 PROC
182 EXPORT UsageFault_Handler [WEAK]
183 B .
184 ENDP
185 SVC_Handler PROC
186 EXPORT SVC_Handler [WEAK]
187 B .
188 ENDP
189 DebugMon_Handler\
190 PROC
191 EXPORT DebugMon_Handler [WEAK]
192 B .
193 ENDP
194 PendSV_Handler PROC
195 EXPORT PendSV_Handler [WEAK]
196 B .
197 ENDP
198 SysTick_Handler PROC
199 EXPORT SysTick_Handler [WEAK]
200 B .
201 ENDP
202
203 Default_Handler PROC
204
205 EXPORT WWDG_IRQHandler [WEAK]
206 EXPORT PVD_IRQHandler [WEAK]
207 EXPORT TAMPER_IRQHandler [WEAK]
208 EXPORT RTC_IRQHandler [WEAK]
209 EXPORT FLASH_IRQHandler [WEAK]
210 EXPORT RCC_IRQHandler [WEAK]
211 EXPORT EXTI0_IRQHandler [WEAK]
212 EXPORT EXTI1_IRQHandler [WEAK]
213 EXPORT EXTI2_IRQHandler [WEAK]
214 EXPORT EXTI3_IRQHandler [WEAK]
215 EXPORT EXTI4_IRQHandler [WEAK]
216 EXPORT DMA1_Channel1_IRQHandler [WEAK]
217 EXPORT DMA1_Channel2_IRQHandler [WEAK]
218 EXPORT DMA1_Channel3_IRQHandler [WEAK]
219 EXPORT DMA1_Channel4_IRQHandler [WEAK]
220 EXPORT DMA1_Channel5_IRQHandler [WEAK]
221 EXPORT DMA1_Channel6_IRQHandler [WEAK]
222 EXPORT DMA1_Channel7_IRQHandler [WEAK]
223 EXPORT ADC1_IRQHandler [WEAK]
224 EXPORT EXTI9_5_IRQHandler [WEAK]
225 EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
226 EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
227 EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
228 EXPORT TIM1_CC_IRQHandler [WEAK]
229 EXPORT TIM2_IRQHandler [WEAK]
230 EXPORT TIM3_IRQHandler [WEAK]
231 EXPORT TIM4_IRQHandler [WEAK]
232 EXPORT I2C1_EV_IRQHandler [WEAK]
233 EXPORT I2C1_ER_IRQHandler [WEAK]
234 EXPORT I2C2_EV_IRQHandler [WEAK]
235 EXPORT I2C2_ER_IRQHandler [WEAK]
236 EXPORT SPI1_IRQHandler [WEAK]
237 EXPORT SPI2_IRQHandler [WEAK]
238 EXPORT USART1_IRQHandler [WEAK]
239 EXPORT USART2_IRQHandler [WEAK]
240 EXPORT USART3_IRQHandler [WEAK]
241 EXPORT EXTI15_10_IRQHandler [WEAK]
242 EXPORT RTCAlarm_IRQHandler [WEAK]
243 EXPORT CEC_IRQHandler [WEAK]
244 EXPORT TIM12_IRQHandler [WEAK]
245 EXPORT TIM13_IRQHandler [WEAK]
246 EXPORT TIM14_IRQHandler [WEAK]
247 EXPORT TIM5_IRQHandler [WEAK]
248 EXPORT SPI3_IRQHandler [WEAK]
249 EXPORT UART4_IRQHandler [WEAK]
250 EXPORT UART5_IRQHandler [WEAK]
251 EXPORT TIM6_DAC_IRQHandler [WEAK]
252 EXPORT TIM7_IRQHandler [WEAK]
253 EXPORT DMA2_Channel1_IRQHandler [WEAK]
254 EXPORT DMA2_Channel2_IRQHandler [WEAK]
255 EXPORT DMA2_Channel3_IRQHandler [WEAK]
256 EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
257 EXPORT DMA2_Channel5_IRQHandler [WEAK]
258
259 WWDG_IRQHandler
260 PVD_IRQHandler
261 TAMPER_IRQHandler
262 RTC_IRQHandler
263 FLASH_IRQHandler
264 RCC_IRQHandler
265 EXTI0_IRQHandler
266 EXTI1_IRQHandler
267 EXTI2_IRQHandler
268 EXTI3_IRQHandler
269 EXTI4_IRQHandler
270 DMA1_Channel1_IRQHandler
271 DMA1_Channel2_IRQHandler
272 DMA1_Channel3_IRQHandler
273 DMA1_Channel4_IRQHandler
274 DMA1_Channel5_IRQHandler
275 DMA1_Channel6_IRQHandler
276 DMA1_Channel7_IRQHandler
277 ADC1_IRQHandler
278 EXTI9_5_IRQHandler
279 TIM1_BRK_TIM15_IRQHandler
280 TIM1_UP_TIM16_IRQHandler
281 TIM1_TRG_COM_TIM17_IRQHandler
282 TIM1_CC_IRQHandler
283 TIM2_IRQHandler
284 TIM3_IRQHandler
285 TIM4_IRQHandler
286 I2C1_EV_IRQHandler
287 I2C1_ER_IRQHandler
288 I2C2_EV_IRQHandler
289 I2C2_ER_IRQHandler
290 SPI1_IRQHandler
291 SPI2_IRQHandler
292 USART1_IRQHandler
293 USART2_IRQHandler
294 USART3_IRQHandler
295 EXTI15_10_IRQHandler
296 RTCAlarm_IRQHandler
297 CEC_IRQHandler
298 TIM12_IRQHandler
299 TIM13_IRQHandler
300 TIM14_IRQHandler
301 TIM5_IRQHandler
302 SPI3_IRQHandler
303 UART4_IRQHandler
304 UART5_IRQHandler
305 TIM6_DAC_IRQHandler
306 TIM7_IRQHandler
307 DMA2_Channel1_IRQHandler
308 DMA2_Channel2_IRQHandler
309 DMA2_Channel3_IRQHandler
310 DMA2_Channel4_5_IRQHandler
311 DMA2_Channel5_IRQHandler
312 B .
313
314 ENDP
315
316 ALIGN
317
318 ;*******************************************************************************
319 ; User Stack and Heap initialization
320 ;*******************************************************************************
321 IF :DEF:__MICROLIB
322
323 EXPORT __initial_sp
324 EXPORT __heap_base
325 EXPORT __heap_limit
326
327 ELSE
328
329 IMPORT __use_two_region_memory
330 EXPORT __user_initial_stackheap
331
332 __user_initial_stackheap
333
334 LDR R0, = Heap_Mem
335 LDR R1, =(Stack_Mem + Stack_Size)
336 LDR R2, = (Heap_Mem + Heap_Size)
337 LDR R3, = Stack_Mem
338 BX LR
339
340 ALIGN
341
342 ENDIF
343
344 END
345
346 ;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****