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comparison lcd.c @ 3:74e9b3baac1e

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Jumbo commit to make things work. Note I have t
author Daniel O'Connor <darius@dons.net.au>
date Sun, 01 Jan 2012 11:01:13 +1030
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children 2c87e30c982d
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2:274e01fa5a4c 3:74e9b3baac1e
1 /*
2 * Example code (I think)
3 * ~/projects/STM32Strive/奋斗STM32开发板例程/奋斗STM32开发板例程/奋斗STM32开发板MINI/STM32奋斗版ucOS II V2.86 uCGUI 3.9 DEMO-V2/STM32奋斗版ucOS II V2.86 uCGUI 3.9 DEMO
4 *
5 * Schematics
6 * Main board ~/Downloads/Strive\ Mini\ STM32\ Schematic.pdf
7 * LCD board ~/Downloads/Strive Mini LCD STM32 Schematic.pdf
8 * MCU reference manual
9 * ~/Downloads/CD00171190.pdf
10 * MCU Data sheet (pinout)
11 * ~/Downloads/CD00191185.pdf
12 * LCD data sheet
13 *
14 */
15 /* LCD board MCU
16 1 VCC
17 2 TC_SCK PA5/SPI1_SCK
18 3 GND
19 4 TC_CS PB7/SPI1_CS3
20 5 RST PE1 FSMC_NBL1? (unlikely)
21 6 TC_DIN PA7/SPI1_MOSI
22 7 nOE PD4/FSMC_nOE
23 8 TC_DOUT PA6/SPI1_MISO
24 9 nWR PD5/FSMC_nWE
25 10 TC_INT PB6
26 11 CS PD7/FSMC_NE1/FSMC_NCE2
27 12 NC
28 13 RS PD11/FSMC_A16
29 14 NC
30 15 D7 PE10/FSMC_D7
31 16 NC
32 17 D6 PE9/FSMC_D6
33 18 NC
34 19 D3 PD1/FSMC_D3
35 20 D13 PD8/FSMC_D13
36 21 D5 PE8/FSMC_D5
37 22 D12 PE15/FSMC_D12
38 23 D4 PE7/FSMC_D4
39 24 GND
40 25 NC
41 26 D11 PE14/FSMC_D11
42 27 D2 PD0/FSMC_D2
43 28 D10 PE13/FSMC_D10
44 29 D1 PD15/FSMC_D1
45 30 D9 PE12/FSMC_D9
46 31 D0 PD14/FSMC_D0
47 32 D14 PD9/FSMC_D9
48 33 NC
49 34 D8 PE11/FSMC_D8
50 35 NC
51 36 NC
52 37 NC
53 38 LCD_PWM PD13/TIM4_CH2
54 39 NC
55 40 D15 PD10/FSMC_D15
56 */
57
58 #include "stm32f10x.h"
59 #include "lcd.h"
60
61 void
62 LCD_init(void) {
63 GPIO_InitTypeDef GPIO_InitStructure;
64 FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
65 FSMC_NORSRAMTimingInitTypeDef p;
66
67 /* Configures LCD Control lines (FSMC Pins) in alternate function Push-Pull mode.
68 *
69 * PD0(D2), PD1(D3), PD4(NOE), PD5(NWE), PD7(NE1/CS), PD8(D13), PD9(D14),
70 * PD10(D15), PD11(A16/RS) PD14(D0), PD15(D1)
71 */
72 GPIO_InitStructure.GPIO_Pin = (GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_7 |
73 GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_14 | GPIO_Pin_15);
74 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
75 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
76 GPIO_Init(GPIOD, &GPIO_InitStructure);
77
78 /* PE7(D4), PE8(D5), PE9(D6), PE10(D7), PE11(D8), PE12(D9), PE13(D10),
79 * PE14(D11), PE15(D12)
80 */
81 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
82 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
83 GPIO_Init(GPIOE, &GPIO_InitStructure);
84
85 /* Configures the Parallel interface (FSMC) for LCD (Parallel mode) */
86 /* FSMC_Bank1_NORSRAM4 timing configuration */
87 p.FSMC_AddressSetupTime = 1;
88 p.FSMC_AddressHoldTime = 0;
89 p.FSMC_DataSetupTime = 2;
90 p.FSMC_BusTurnAroundDuration = 0;
91 p.FSMC_CLKDivision = 0;
92 p.FSMC_DataLatency = 0;
93 p.FSMC_AccessMode = FSMC_AccessMode_A;
94
95 /* FSMC_Bank1_NORSRAM4 configured as follows:
96 - Data/Address MUX = Disable
97 - Memory Type = SRAM
98 - Data Width = 16bit
99 - Write Operation = Enable
100 - Extended Mode = Disable
101 - Asynchronous Wait = Disable */
102 FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM4;
103 FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
104 FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
105 FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
106 FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
107 FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
108 FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
109 FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
110 FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
111 FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
112 FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
113 FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
114 FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
115 FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
116 FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
117
118 FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
119
120 /* Enable FSMC_Bank1_NORSRAM4 */
121 FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE);
122 }